AM5728 datasheet(131/415 Pages) TI1

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AM5729, AM5728, AM5726

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SPRS953F – DECEMBER 2015 – REVISED MAY 2019

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Terminal Configuration and Functions

4.4.15 Peripheral Component Interconnect Express (PCIe)

NOTE

For more information, see the Serial Communication Interfaces / PCIe Controllers and the

Shared PHY Component Subsystems / PCIe Shared PHY Subsystem sections of the device

TRM.

Table 4-18. PCIe Signal Descriptions

SIGNAL NAME

DESCRIPTION

TYPE

BALL

pcie_rxn0

PCIe1_PHY_RX Receive Data Lane 0 (negative) - mapped to PCIe_SS1 only.

IDS

AG13

pcie_rxp0

PCIe1_PHY_RX Receive Data Lane 0 (positive) - mapped to PCIe_SS1 only.

IDS

AH13

pcie_txn0

PCIe1_PHY_TX Transmit Data Lane 0 (negative) - mapped to PCIe_SS1 only.

ODS

AG14

pcie_txp0

PCIe1_PHY_TX Transmit Data Lane 0 (positive) - mapped to PCIe_SS1 only.

ODS

AH14

pcie_rxn1

PCIe2_PHY_RX Receive Data Lane 1 (negative) - mapped to either PCIe_SS1

(dual lane- mode) or PCIe_SS2 (single lane- mode)

IDS

AG11

pcie_rxp1

PCIe2_PHY_RX Receive Data Lane 1 (positive) - mapped to either PCIe_SS1

(dual lane- mode) or PCIe_SS2 (single lane- mode)

IDS

AH11

pcie_txn1

PCIe2_PHY_TX Transmit Data Lane 1 (negative) - mapped to either PCIe_SS1

(dual lane- mode) or PCIe_SS2 (single lane- mode)

ODS

AG12

pcie_txp1

PCIe2_PHY_TX Transmit Data Lane 1 (positive) - mapped to either PCIe_SS1

(dual lane- mode) or PCIe_SS2 (single lane- mode)

ODS

AH12

ljcb_clkp

PCIe1_PHY / PCIe2_PHY shared Reference Clock Input / Output Differential Pair

(positive)

IODS

AG15

ljcb_clkn

PCIe1_PHY / PCIe2_PHY shared Reference Clock Input / Output Differential Pair

(negative)

IODS

AH15

4.4.16 Controller Area Network Interface (DCAN)

NOTE

For more information, see the Serial Communication Interface / DCAN section of the device

TRM.

Table 4-19. DCAN Signal Descriptions

SIGNAL NAME

DESCRIPTION

TYPE

BALL

DCAN 1

dcan1_tx

DCAN1 transmit data pin

G20

dcan1_rx

DCAN1 receive data pin

G19/ AD17

DCAN 2

dcan2_tx

DCAN2 transmit data pin

E21/ B21

dcan2_rx

DCAN2 receive data pin

F20/ AC17/ B20

4.4.17 Ethernet Interface (GMAC_SW)

CAUTION

The I/O timings provided in Section 7, Timing Requirements and Switching

Characteristics are valid only if signals within a single IOSET are used. The

IOSETs are defined in the Table 7-72, Table 7-75, Table 7-80 and Table 7-87.

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