CS5340

DS601PP2

17

4 APPLICATIONS

4.1

Single, Double, and Quad Speed Modes

The CS5340 can support output sample rates from 2 kHz to 200 kHz. The proper speed mode can be determined

by the desired output sample rate and the external MCLK/LRCK ratio, as shown in Table 1.

* Quad Speed Mode, 64x only available in Master Mode.

Table 1. Speed Modes and the Associated Output Sample Rates (Fs)

4.2

Operation as Either a Clock Master or Slave

The CS5340 supports operation as either a clock master or slave. As a clock master, the LRCK and SCLK pins are

outputs with the left/right and serial clocks synchronously generated on-chip. As a clock slave, the LRCK and SCLK

pins are inputs and require the left/right and serial clocks to be externally generated. The selection of clock master

or slave is made via the Mode pins as shown in Table 2.

Speed Mode

MCLK/LRCK

Ratio

Output Sample Rate Range (kHz)

Single Speed Mode

512x

43 - 54

256x

2 - 54

Double Speed Mode

256x

86 - 108

128x

50 - 108

Quad Speed Mode

128x

172 - 200

64x*

100 - 200

M1 (Pin 16)

M0 (Pin 1)

MODE

0

0

Clock Master, Single Speed Mode

0

1

Clock Master, Double Speed Mode

1

0

Clock Master, Quad Speed Mode

1

1

Clock Slave, All Speed Modes

Table 2. CS5340 Mode Control