CS5340

DS601PP2

19

4.2.3

Master Clock

The CS5340 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters. There is

also an internal MCLK divider which is automatically activated based on the speed mode and frequency of the

MCLK. Table 3 shows a listing of the external MCLK/LRCK ratios that are required. Table 4 lists some common au-

dio output sample rates and the required MCLK frequency. Please note that not all of the listed sample rates are

supported when operating with a fast MCLK (512x, 256x, 128x for Single, Double, and Quad Speed Modes respec-

tively).

4.3

Serial Audio Interface

level on SDOUT (pin 4). A 10 k

needed to select Left Justified format. Please see Figures 13 through 16 on page 14, for more information on the

required timing for the two serial audio interface formats.

Single Speed Mode

Double Speed Mode

Quad Speed Mode

MCLK/LRCK Ratio

256x, 512x

128x, 256x

64x*,128x

* Quad Speed, 64x only available in Master Mode.

Table 3. Master Clock (MCLK) Ratios

SAMPLE RATE (kHz)

MCLK (MHz)

32

8.192

44.1

11.2896

22.5792

48

12.288

24.576

64

8.192

88.2

11.2896

22.5792

96

12.288

24.576

192

12.288

24.576

Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates

SD AT A

2 3 22

7

6

23 2 2

SC L K

LRCK

23 22

54

32

10

8

76

54

32

10

8

9

9

Left C h annel

R igh t C h a nne l

Figure 19. Left-Justified Serial Audio Interface

SD A T A

2 3 2 2

8

7

23 2 2

SC LK

L RCK

23 22

65

43

21

0

87

65

43

21

0

9

9

Le ft C h annel

R ight C hannel