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ADUCM331WFS Datasheet(PDF) 10 Page - Analog Devices |
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ADUCM331WFS Datasheet(HTML) 10 Page - Analog Devices |
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10 / 17 page  ADuCM330WFS/ADuCM331WFS Data Sheet Rev. A | Page 10 of 17 TA = −40°C to +115°C TA = +115°C to +125°C1 Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit LIN AC PARAMETERS1 Bus load conditions (CBUS||RBUS): 1 nF||1 kΩ or 6.8 nF||660 Ω or 10 nF||500 Ω Duty Cycle 1 (D1) Threshold recessive maximum (THREC(MAX)) = 0.744 × VBAT, threshold dominant maximum (THDOM(MAX)) = 0.581 × VBAT, supply voltage at transceiver (VSUP) = 6.0 V to 19 V, tBIT = 50 µs, D1 = tBUS_REC(MIN)/(2 × tBIT) 0.396 Duty Cycle 2 (D2) Threshold recessive minimum (THREC(MIN)) = 0.284 × VBAT, threshold dominant minimum (THDOM(MIN)) = 0.422 × VBAT, VSUP = 6.0 V to 19 V, tBIT = 50 µs, D2 = tBUS_REC(MAX)/(2 × tBIT) 0.581 Duty Cycle 3 (D3)23 THREC(MAX) = 0.778 × VBAT, THDOM(MAX) = 0.616 × VBAT, VDD = 6.0 V to 19 V, tBIT = 96 µs, D3 = tBUS_REC(MIN)/(2 × tBIT) 0.417 Duty Cycle 4 (D4)23 THREC(MIN) = 0.389 × VBAT, THDOM(MIN) = 0.251 × VBAT, VDD = 6.0 V to 19 V, tBIT = 96 µs, D4 = tBUS_REC(MAX)/(2 × tBIT) 0.590 Propagation Delay of Receiver (tRX_PD)23 6 µs Symmetry of Receiver Propagation Delay Rising Edge (tRX_SYM)23 With respect to falling edge (tRX_SYM = propagation delay rising edge (tRX_PDR) − propagation delay falling edge (tRX_PDF)) −2 +2 µs POWER REQUIREMENTS Power Supply Voltages VDD (Pin 26) 3.6 19 V DVDD33 (Pin 21) 3.3 3.3 V AVDD18 (Pin 19) 1.88 1.88 V DVDD18 (Pin 22) 1.88 1.88 V POWER CONSUMPTION Supply Current (IDD) Processor, Normal Mode24 Clock Divider Setting 0 (CD0) (peripheral clock (PCLK) = 16 MHz), 16 MHz 1% mode, ADCs off, reference buffer off, executing code from program flash 8 17 9 mA Clock Divider Setting 1 (CD1) (PCLK = 8 MHz), 16 MHz 1% mode, ADCs off, reference buffer off, executing code from program flash 6 7 mA CD0 (PCLK = 16 MHz), 16 MHz 1% mode, ADCs on, reference buffer on, executing code from program flash 9.5 18.5 10 mA IDD Processor, Powered Down Precision oscillator off, ADC off, external LIN master pull-up resistor present, measured with wake-up and watchdog timers clocked from low power oscillator, maximum value is at 105°C, and VDD = 18 V 55 100 µA IDD LIN 500 µA IDD Current Channel ADC (IADC) Gain = 4, 8, or 16 700 µA Gain = 32 or 64 800 µA Low power mode, gain = 64 350 µA |
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