• 10 •

b7

———

AE

———

AE= 0; weekday alarm is enabled.

———

AE= 1; weekday alarm is disabled.

b6..0

<Weekday alarm>

These bits represents the weekday alarm information

value 0 to 6.

2.7.6 CLKOUT frequency register

Table 23 CLKOUT frequency register bits description

0DH

Symbol

Description

b7

FE

FE = 0; the CLKOUT output is inhibited and the CLKOUT output is set to

high-impedance. FE = 1; the CLKOUT output is activated.

b6..2

-

not implemented

b1

FD1

Table 24.

b0

FD0

Table 24 CLKOUT frequency selection

FD1

FD0

0

0

32.768 kHz

01

1 024 Hz

10

32 Hz

11

1 Hz

2.7.7 Countdown timer registers

The Timer register is an 8-bit binary countdown timer. It is enabled and disabled via the

Timer control register bit TE. The source clock for the timer is also selected by the Timer

control register. Other timer properties, e.g. interrupt generation, are controlled via the

SCL must be operating at a frequency of at least twice the selected timer clock.

Table 25 Timer control register bits description

0EH

Symbol

Description

b7

TE

TE = 0; timer is disabled. TE = 1; timer is enabled.

b6～b2

-

not implemented

b1

TD1

Timer source clock frequency selection bits. These bits

determine the source clock for the countdown timer, see

Table 26. When not in use, TD1 and TD0 should be set to

b0

TD0

Table 26 Timer source clock frequency selection

TD[1:0]

Timer source clock

frequency（Hz）

HM8563