SDIO Connector

(3.3V IO)

SD Controller

(1.8V IO)

LSF0108

SDIO level translator

Device PCB

TP1

TP2

GND

Vref_A

EN

Vref_B

A1

A2

B1

B2

LSF0102

Short Signal Trace as possible

Minimize Stub as possible

1

2

3

4

5

6

7

8

16

LSF0101, LSF0102, LSF0108

SDLS966H – DECEMBER 2013 – REVISED JUNE 2019

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Product Folder Links: LSF0101 LSF0102 LSF0108

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Copyright © 2013–2019, Texas Instruments Incorporated

(1)

Vref_A is required to be the lowest voltage level across all inputs and outputs.

10 Power Supply Recommendations

There are no power sequence requirements for the LSF family. For recommended operating voltages for all

supply and input pins, see Table 6.

Table 6. Recommended Operating Voltages

PARAMETER

MIN

TYP

MAX

UNIT

reference voltage (A)

0.95

4.5

V

Vref_B

reference voltage (B)

Vref_A + 0.8

5.5

V

input voltage on EN pin

Vref_A + 0.8

5.5

V

Vpu

pull-up supply voltage

0

Vref_B

V

11 Layout

11.1 Layout Guidelines

Because the LSF family is a switch-type level translator, the signal integrity is highly related with a pull-up

resistor and PCB capacitance condition.

•

Short signal trace as possible to reduce capacitance and minimize stub from pull-up resistor.

•

Place LSF close to high voltage side.

•

Select the appropriate pull-up resistor that applies to translation levels and driving capability of transmitter.

11.2 Layout Example

Figure 9. Short Trace Layout

Figure 10. Device Placement