TSB17BA1

IEEE STD 1394b SINGLEPORT CABLE TRANSCEIVER

SLLS568C − JANUARY 2004 − REVISED MARCH 2004

1

POST OFFICE BOX 655303

1394b-2002 at S100B Signaling Rates

1394b Signaling Across Unshielded

Twisted Pair Category 5 (UTP5 or CAT5)

Cable or Better at 100 Megabits per Second

(Mbits/s)

in Battery Powered Applications

Dual 3.3-V/1.8-V Supply Operation

TSSOP Package

Power States When Data Is Not Being

Driven

description

The TSB17BA1 is a single-port 100-Mbps transceiver used in transporting IEEE Std 1394b (1394b) or other

coded data across CAT5 or better cabling. It is attached to a 1394b-capable port on a 1394b physical layer (PHY)

to enable 1394b 100-Mbps signals to be transmitted and received across up to 100 meters of unshielded

twisted-pair category 5 (UTP5) cable. Equalization is applied to the signal received from the UTP5 cable to boost

signal-to-noise ratio (SNR) to allow sensing of the data. A 1394b PHY device capable of transmitting at only

100 Mbits/s in 1394b-only mode is required for correct functionality. This PHY must be connected to the

TSB17BA1 at one of the twisted-pair (TP) ports, with the 110-

Ω 1394b transmission line properly terminated.

The TSB17BA1 must then be connected to a 100-

Ω transmission line properly terminated and connected to an

isolating transformer. This transformer is then connected to an RJ45 connector. All of the parameters on the

UTP5 side of the TSB17BA1 are set the same as 100baseT Ethernet. This allows the mechanical and magnetic

infrastructure, which is used to design a 100baseT connection, to be used when designing a 100-Mbits/s UTP5

1394b connection. This device does not implement the autocrossover functionality described in chapter 12 of

IEEE Std 1394b-2002. This means the required crossover of TPA to TPB and TPB to TPA must be done in the

cable or connector or PWB; in other words, a mechanical crossover must be implemented (see the Application

Information section).

terminal assignments

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

E_OUT

E_INN

E_INP

VSS33

BETA_OUTP

BETA_OUTN

VDD33

BETA_INP

BETA_INN

PD_SE

TEST0

TEST1

VREG_PD

VCONTROL

R1

R0

UTP5_INP

UTP5_INN

VDDCORE

UTP5_OUTP

UTP5_OUTN

VSSCORE

TEST3

TEST2

PW PACKAGE

(TOP VIEW)

Copyright

 2004, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Implements technology covered by one or more patents of Apple Computer, Inc. and SGS Thompson, Limited.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.