PT4301

V1.4

3

October 2010

ORDER INFORMATION

Valid Part Number

Package Type

Top Code

PT4301-X

24 Pins, SSOP, 150mil

PT4301-X

PIN CONFIGURATION

PIN DESCRIPTION

Pin Name

I/O

Description

Pin No.

XOUT

O

Crystal oscillator output

1

REGIF

P

Supply voltage for IF portion

2

LNAIN

I

LNA input

3

VSSLNA

G

Ground for LNA

4

LNAOUT

O

LNA output

5

REGRF

P

Supply voltage for RF portion

6

MIXIN

I

Mixer input

7

VSSMIX

G

Ground for image-rejection mixer

8

MIXOUT

O

Mixer output

9

VSSDIG

G

Ground for LO and digital portions

10

REGDIG

P

Supply voltage for LO and digital portions

11

AGCDIS

I

AGC control pin. Pull high (connect to VDD5) to disable AGC

12

LIMIN

I

Limiting amplifier input

13

LIMINB

I

Limiter amplifier de-coupling input

14

DFO

O

Data filter output

15

DSN

I

Negative data slicer input

16

OPP

I

Non-inverting op-amp input for Sallen-Key data filter

17

DFFB

I/O

Data filter feedback node

18

DSP

I

Positive data slicer input

19

VDD5

P

5V supply voltage

20

DATA

O

Data output

21

PDOUT

O

Peak detector output

22

CE

I

Chip enable pin. Pull high (connect to VDD5) to power on the chip

23

XIN

I

Crystal oscillator input

24

Note: Pin 13 and Pin 14 are identical pins. Users can choose either pin as the limiting amplifier input and treat the other pin as the de-coupling input.