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ADS8381IPFBTG4 Datasheet(PDF) 13 Page - Texas Instruments |
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ADS8381IPFBTG4 Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 35 page ![]() ADS8381 SLAS364D − APRIL 2002 − REVISED FEBRUARY 2005 www.ti.com 13 †Signal internal to device tw1 tw2 tpd1 tpd2 tw4 tCONV tw3 tCONV t(ACQ) th1 th1 CONVST BUSY CS = 0 SAMPLING† (When CS = 0) BYTE CONVERT† tdis tsu5 tsu5 tpd3 tpd3 tHOLD tHOLD tsu(AB) tsu(AB) td5 BUS 18/16 RD = 0 DB[17:12] D[17:12] D[9:4] DB[11:10] D[11:10] DB[9:0] D[9:0] D[3:2] Next D[17:12] Next D[11:10] Next D[9:0] D[1:0] tsu5 tsu5 Previous D[1:0] Figure 4. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND—Auto Read |
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