UPD75P316B datasheet(21/42 Pages) NEC

21 / 42 page

µPD75P316A

Time required for oscillation to become stabilized after VDD reaches MIN. of the oscillation voltage range or after

STOP made release.

Note

When the main system clock and subsystem clock oscillation circuit are used, the area enclosed by dotted

line in the figure should be wired as follows to prevent influence from the wiring capacitance, etc..

• Wiring should be as short as possible.

• Do not cross other signal lines.

Do not place the circuit closed to a line in which varying high current flows.

• The connecting point of oscillation circuit capacitor should always be the same potential as VDD. Do

not connect it to the power supply pattern in which high current flows.

• Do not pick up a signal from the oscillation circuit.

The subsystem clock oscillation circuit is designed to be low amplification circuit for low dissipation

current, thus misoperation due to noise occurs more often than with the main system clock oscillation

circuit. Therefore, when the subsystem clock is used, care is needed especially for the wiring procedure.

UPD75P316B Datasheet(PDF) 21 Page - NEC