AD5620/AD5640/AD5660

Rev. A | Page 9 of 24

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

SYNC

GND

8

DIN

7

SCLK

6

5

AD5620/

AD5640/

AD5660

TOP VIEW

(Not to Scale)

Figure 3. SOT-23 Pin Configuration

SYNC

GND

8

DIN

7

SCLK

6

5

AD5620/

AD5640/

AD5660

TOP VIEW

(Not to Scale)

Figure 4. MSOP Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

2

Reference Voltage Output.

3

4

Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.

5

SYNC

Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When

SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following

AD5620/AD5640 unless SYNC is taken high before this edge. In this case, the rising edge of SYNC acts as an

interrupt, and the write sequence is ignored by the DAC.

6

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data

can be transferred at rates up to 30 MHz.

7

DIN

Serial Data Input. The AD5660 has a 24-bit shift register, and the AD5620/AD5640 have a 16 -bit shift register.

Data is clocked into the register on the falling edge of the serial clock input.

8

GND

Ground Reference Point for all circuitry on the part.