5

Figure 5a. Receiver section timing (dual receive clocks).

Timing Characteristics for Gigabit Ethernet – Receiver Section

T = 0

Symbol

Parameter

Units

Min.

Typ.

Max.

f_lock

Frequency Lock at Powerup

µs

500

Bit Sync Time

bits

2500

RX [0:3][0:9] Output Setup Time (Data Valid Before Clock)

ns

2.5

RX [0:3][0:9] Output Hold Time (Data Valid After Clock)

ns

2.0

RC [0:3][0] and RC [0:3][1] Duty Cycle

%

40

60

Rising Edge Time Difference between RBC0 and RBC1 (Half Rate) ns

7.5

8.5

Receiver Latency

ns

20.7

bits

26.0

Notes:

1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3.

3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the

edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, RC[0:1]).

DATA

DATA

RX [0:3] [0:9]

RC [0:3] [1]

DATA

DATA

1.4 V

2.0 V

0.8 V

SYNC

RC [0:3] [0]

2.0 V

0.8 V

1.4 V

K28.5+

Timing Characteristics for Fibre Channel – Receiver Section

T = 0

Symbol

Parameter

Units

Min.

Typ.

Max.

f_lock

Frequency Lock at Powerup

µs

500

Bit Sync Time

bits

2500

RX [0:3][0:9] Output Setup Time (Data Valid Before Clock)

ns

3.0

RX [0:3][0:9] Output Hold Time (Data Valid After Clock)

ns

1.5

RC [0:3][0] and RC [0:3][1] Duty Cycle

%

40

60

Rising Edge Time Difference between RBC0 and RBC1 (Half Rate) ns

8.9

9.9

Receiver Latency

ns

22.4

bits

28.0

Notes:

1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3.

3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the

edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, RC[0:1]).