RTH010 DATA SHEET REV F
The product specifications contained in this data sheet are subject to change. Rockwell Scientific Company reserves the right to make changes to its product
specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use.
Page
4
Test Levels
TEST LEVEL
TEST PROCEDURE
1
100% production tested at Ta = 25 C
1
2
Sample tested at Ta = 25 C unless other temperature is specified
1
3
Quaranteed by design and/or characterization testing
4
Typical value only
1
All tests are continuous, not pulsed. Therefore, Tj (junction temperature) > Tc (case temperature) > Ta (ambient temperature).
This is the normal operating condition and is more stressful than a pulsed test condition.
Pin Description and Pin Out
P/I/O
NAME
FUNCTION
P
GND
Power Supply Ground
I
TMS
Track Mode Select
I
INP
Analog Input
O
OUTP
Analog Output
I
CLK1
Clock Input 1, High = Track Mode
I
CLK2
Clock Input 2, High = Track Mode
P
VEE
Negative Power Supply, -5.2V ± 5%
P
VCC
Positive Power Supply, 5.0V ± 5%
I
INN
Complementary Analog Input
O
OUTN
Complementary Analog Output
I
CLK1B
Complementary Clock Input 1
I
CLK1B
Complementary Clock Input 2
Definitions of Terms
Acquisition Time (tacq). The delay between
the time that a track-and-hold circuit (TH) enters
track mode and the time that the TH hold
capacitor nodes track the input within some
specified precision. The acquisition time sets a
lower limit on the required track time during
clocked operation.
Aperture Delay (ta). The average (or mean
value) of the delay between the hold command
(input clock switched from track to hold state)
and the instant at which the analog input is
sampled. The time is positive if the clock path
delay is longer than the signal path delay. It is
negative if the signal path delay is longer than
the clock path delay.
Aperture Jitter (
∆t). The standard deviation of
the delay between the hold command (input
clock switched from hold to track state) and the
instant at which the analog input is sampled,
excluding clock source jitter. It is the total jitter if
the clock source is jitter free (ideal). Jitter
diverges slowly as measurement time increases
because of “1/f” noise, important at low
frequencies (< 10 kHz). The specified jitter takes
into account the white noise sources only
(thermal and shot noise). For high-speed
samplers this is reasonable, since even long
data records span a time shorter than the time
scale important for 1/f noise. For white-noise
caused jitter, the clock and aperture jitter can be
added in an rms manner to obtain the total
sampling jitter.
Figure 2. Pin configuration (top
view, not to scale)24-lead glass-wall
metallized ceramic quad flat pack
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