HD64F2145 datasheet(347/829 Pages) RENESAS

347 / 829 page

Rev. 2.0, 08/02, page 307 of 788

13.3.4

Edge Sense Register (SEDGR)

SEDGR detects a rising edge on the timer connection input pins and the occurrence of 2fH

modification, and determines the phase of the IVI and IHI signals.

Bit

Bit Name

Initial Value

R/W

Description

VEDG

R/(W)*

VSYNCI Edge

Detects a rising edge on the VSYNCI pin.

[Clearing condition]

When 0 is written in VEDG after reading VEDG = 1

[Setting condition]

When a rising edge is detected on the VSYNCI pin

HEDG

R/(W)*

HSYNCI Edge

Detects a rising edge on the HSYNCI pin.

[Clearing condition]

When 0 is written in HEDG after reading HEDG = 1

[Setting condition]

When a rising edge is detected on the HSYNCI pin

CEDG

R/(W)*

CSYNCI Edge

Detects a rising edge on the CSYNCI pin.

[Clearing condition]

When 0 is written in CEDG after reading CEDG = 1

[Setting condition]

When a rising edge is detected on the CSYNCI pin

HFEDG

R/(W)*

HFBACKI Edge

Detects a rising edge on the HFBACKI pin.

[Clearing condition]

When 0 is written in HFEDG after reading HFEDG = 1

[Setting condition]

When a rising edge is detected on the HFBACKI pin

VFEDG

R/(W)*

VFBACKI Edge

Detects a rising edge on the VFBACKI pin.

[Clearing condition]

When 0 is written in VFEDG after reading VFEDG = 1

[Setting condition]

When a rising edge is detected on the VFBACKI pin

HD64F2145 Datasheet(PDF) 347 Page - Renesas Technology Corp

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