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HD64F2145 Datasheet(PDF) 375 Page - Renesas Technology Corp

Part # HD64F2145
Description  Hitachi 16-Bit Single-Chip Microcomputer
PDF  829 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F2145 Datasheet(HTML) 375 Page - Renesas Technology Corp

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Rev. 2.0, 08/02, page 335 of 788
14.4.3
5(62
5(62
5(62
5(62 Signal Output Timing
When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the
RST/
10, bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time,
the low level signal is output from the
5(62 pin. The timing is shown in figure 14.5.
ø
TCNT
H'FF
H'00
132 states
518 states
Overflow signal
(internal signal)
OVF
signal
Internal reset
signal
Figure 14.5 Output Timing of
5(62
5(62
5(62
5(62 signal
14.5
Interrupt Sources
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
When the NMI interrupt request is selected in watchdog timer mode, an NMI interrupt request is
generated by an overflow.
Table 14.2
WDT Interrupt Source
Name
Interrupt Source
Interrupt Flag
DTC Activation
WOVI
TCNT overflow
OVF
Not possible



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