STR720 datasheet(117/401 Pages) STMICROELECTRONICS

117 / 401 page

STR720 - EXTERNAL MEMORY INTERFACE (EMI)

117/401

This means that for memory banks 0 and 1 setup and hold times (measured in EMI internal

clock units) are fixed.

Table 32 resumes the write cycle timing configurations.

For read cycles which translate in a single external bus operation (e.g. a 16-bit read), the total

length (measured in EMI internal clock units) that a single access will require (equal to the

length over which the Chip Select will be active) will also depend on the memory bank the

cycle is executed on. Its total length can be calculated through the formula:

Setup Read Enable Time

Hold

CS Length (Read, Bank 0/1) = 0

+ (C_LENGTH+2)

+ 0

This means that for memory banks 0 and 1 Setup and Hold times (measured in EMI internal

clock units) are fixed to zero.

Table 33 resumes the read cycle timing configurations.

32-bit read or write cycles are translated in 2 external bus cycles so the total external bus

cycle duration can be obtained through the following formula

Total CS Length (Read/Write Bank x) = (Length of the single cyle)*(2).

However it must be noticed that in case of a 32-bit read cycle, resulting in two external bus

accesses, the sampling points used to read data in are not placed symmetrically in the two

halves of the access, as it is illustrated by the following formulas:

Sampling point from valid address

Low word sampling point (Read, Bank 0/1) =

C_LENGTH+2

High word sampling point (Read, Bank 0/1 =

C_LENGTH+1

For a timing diagram example see also Section 11.3.3: Read Access Examples on page 118.

Table 32. EMI Write Timings

Parameter

Field

Bank 0,1

Setup Time

n.a.

WE Time

C_LENGTH

“000”:”111”=1:8 AHB_CLK

Hold Time

n.a.

CS Length

2:9 AHB_CLK

Table 33. EMI Read Timings

Parameter

Field

Bank 0,1

Setup Time

n.a.

RE Time

C_LENGTH

“000”:”111”=2:9 AHB_CLK

Hold Time

n.a.

CS Length

2:9 AHB_CLK

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