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SAM5504B Datasheet(PDF) 17 Page - List of Unclassifed Manufacturers

Part # SAM5504B
Description  AUDIO & MUSIC MULTI-DSP PROCESSOR
PDF  51 Pages
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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SAM5504B Datasheet(HTML) 17 Page - List of Unclassifed Manufacturers

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SAM5504B
SAM5504B.pdf
– Rev 14/05/2018
17
© 2015-2018 Dream S.A.S., France
4.3.4. Host Parallel Interface as primary function
Pin name
Pin#
Type
Mem
Cfg
Description
D0-D1
34,33,
I/O DR8
2
Host parallel interface data. Output if CS/ and RD/ are low
(read from chip), input if CS/ and WR/ are low (write to
chip). Type of data defined by A0 address input.
D2-D7
11,12,
23-26
I/O 5VT
DR12
DAAD2
34
In
2
Stereo audio digital input 2, I2S or MSB format.
DABD4
33
Out DR8
2
Stereo audio digital output 4, I2S or MSB format.
DABD3
11
Out DR12
2
Stereo audio digital output 3, I2S or MSB format.
DABD2
12
Out DR12
2
Stereo audio digital output 2, I2S or MSB format.
XWSBD1
23
In 5VT
2
External word sel. Clock
1 for digital audio inputs
DAAD[7:0].
XCLBD1
24
In 5VT
2
External clock bit 1 for digital audio inputs DAAD[7:0].
XWSBD0
25
In 5VT
2
- External word select clock 0 for digital audio inputs
DAAD[7:0].
- Word Clock input for audio sync. on external clock device.
XCLBD0
26
In 5VT
2
External clock bit for digital audio inputs DAAD[7:0].
P0.0-P0.1
34,33,
I/O DR8
2
General purpose I/O pins. Can be individually programmed
as input or output.
P0.2-P0.7
11,12,
23-26
I/O 5VT
DR12
VIN1-VIN2
34,33
In
2
Analog input 1 and input 2 of embedded ADC.
IRQ
28
Out DR12
2
Host parallel interface mode 0 interrupt request. High when
data is ready to be transferred from chip to host. Reset by a
read from host (CS/=0 and RD/=0).
External 100k max pull-down resistor is needed for safe ROM boot.
SSINT/
28
Out DR12
2
Serial Slave Synchronous Interface data request, active
low.
External 100k max pull-up resistor is needed for safe ROM boot.
P0.8_IntA
28
I/O 5VT
DR12
2
General purpose I/O pin.
External Interrupt source IntA.
A0
29
In 5VT
2
Host parallel interface address 0.
In case A1=0 (mode 0): Indicates data/status or data/ctrl
transfer type (CS/ RD/ low or CS/ WR/ low).
In case A1=1 (mode 1): the A0 input is “don’t care”.
SSCLK
29
In 5VT
2
Serial Slave Synchronous Interface clock input.
P0.10
29
I/O 5VT
DR12
2
General purpose I/O pin.
CS/
50
In 5VT
2
Host parallel interface chip select, active low.
SSYNC
50
In 5VT
2
Serial Slave Synchronous Interface input sync signal.
P0.11
50
I/O 5VT
DR8
2
General purpose I/O pin.
WR/
52
In 5VT
2
Host parallel interface write, active low. D7-D0 data is
sampled by chip on WR/ rising edge if CS/ is low.
SSDIN
52
In 5VT
2
Serial Slave Synchronous Interface input data.
P0.12
52
I/O 5VT
DR8
2
General purpose I/O pin.
RD/
51
In 5VT
2
Host parallel interface read, active low. D7-D0 data is output
when RD/ goes low and CS/ is low.
External 100k max pull-up resistor is needed for safe ROM boot.
MIDI_OUT2
51
Out 5VT
2
Additional Serial MIDI Out (UART Tx)
External 100k max pull-up resistor is needed for safe ROM boot.
P0.13
51
I/O 5VT
DR8
2
General purpose I/O pin.
External 100k max pull-up resistor is needed for safe ROM boot.
If used as input, should not be driven low by external device while
ROM boot.



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