SAM5504B datasheet(34/51 Pages) ETC1

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SAM5504B

SAM5504B.pdf

– Rev 14/05/2018

tcslwrl

CS/

WR/

D[7:0]

tpwr

twrhcsh

tavwrh

tawh

tdvwrh

tdwh

HPI mode 0, write cycle

Parameter

Symbol

Min

Typ

Max

Unit

Chip select low to WR/ low

tcslwrl

WR/ pulse width

tpwr

WR/ high to CS/ high

twrhcsh

Address valid to WR/ high

tavwrh

Data valid to WR/ high

tdvwrh

Address out hold from WR/

tawh

Data out hold from WR/

tdwh

Notes:

1. tcslwrl Min and twrhcsh Min can be reduced to 0 ns if 3 ns are added to tpwr Min, tawh Min,

tdwh Min, tavwrh Min, tdvwrh Min

8.4.1.2.

HPI mode 0, IO Status Register

ID3 ID2 ID1 ID0

Status register is read when A1=0, A0=1, RD/=0, CS/=0

- TE: Transmit Empty: This bit is 1 when nothing is transmitted from SAM5504B to host. If 0, data

from SAM5504B to host is pending and IRQ pin is high. Host reading the data with pin A0=0 sets

TE to 1 and clear IRQ. TE bit is actually reflecting inverted value of IRQ pin (IRQ/).

- RF: Receiver Full: Host should not write any data or control to SAM5504B if this bit is 1. When 0,

then SAM5504B is ready to accept data from host.

- ID[3:0]: these 4 bits are firmware dependant and may be used for defining type of data sent by

SAM5504B in case of multiple flows of data.

Host read should be performed with following steps:

a) Nothing to read if IRQ pin is low. First wait for IRQ pin being high

b) Read status (A0=1) to get ID[3:0] (this step is optional if ID[3:0] bits are not used and not

defined by firmware)

c) Read data (A0=0) (IRQ goes low at the end of read cycle, on rising edge of RD/ signal)

d) Wait for IRQ pin being high again…

Note: On steps a) and d), if IRQ pin is not connected and not used, host can also read status and

wait for TE bit=0

SAM5504B Datasheet(PDF) 34 Page - List of Unclassifed Manufacturers

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