MP3275

7

Rev. 4.00

The MP3275 is easily interfaced to a wide variety of digital

systems. Discussion of the timing requirements of the MP3275

control signals follows.

Figure 1. shows a complete timing diagram for the MP3275

convert start operation.

WR is used to initiate a conversion.

A conversion is started by taking WR low, then high again

(conversion is enabled on the rising edge of WR). There are two

possible conditions that will affect conversion timing.

1. ADEN = 1. At the falling edge of WR, the input channel is

determined by the data present on the address bits. The

track and hold begins to settle after which STL returns low,

indicating that the multiplexer, buffer amp, and sample/hold

have settled to less than 1/2 LSB of final value. If the rising

edge of WR returns high prior to STL going low, conversion

will begin on the falling edge of STL. If the rising edge of WR

is delayed until after STL returns low, the input signal is sam-

pled and the conversion is started at the rising edge of WR

giving the user better control of the sampling time.

2. ADEN = 0. At the falling edge of WR the data present at the

address is ignored and the channel selected during the pre-

vious conversion remains selected. In this case the track

and hold settling time is omitted and STL never goes high. At

the rising edge of WR the input signal is sampled, and con-

version is started.

There are two possible states that the data output could be in

during a conversion.

1. If RD is held high during a conversion the output would re-

main high impedance throughout the conversion. This is the

preferred method of operation as any noise present on SDO

is rejected.

2. If RD is held low during a conversion, the data present SDO

will be from the previous conversion until the present conver-

sion is completed, when STS returns low. The data from the

new conversion will be available through SDO. The state of

RD should not change during a conversion.

Once a conversion is started and the STL or STS line goes

high, convert start commands will be ignored until the conver-

sion cycle is completed. The SDO output buffer cannot be en-

abled during conversion.

In addition, all input and output

changes during conversion can introduce noise, and should be

avoided when possible.

ADC Control Timing

Table 2. ADC Write Timing

(See Figure 1.)

25

Tmin to

Tmax

Limits

Comments/Test Conditions

Address to WR Set-Up Time

0

0

ns min

Address to WR Hold Time

0

0

ns min

WR Pulse Width

80

80

ns min

ADEN to WR Set-Up Time

0

ns min

ADC Conversion Timing

WR to STL

↑ Delay

150

150

ns max

ADEN = 1

STL High (Settling Period)

10

15

µs max

STL to STS Low (Converting)

15

20

µs max

WR to STS High (ADEN = 0)

200

250

ns max

STL = 0 when ADEN = 0

WR to STS Low (ADEN = 1)

15

20

µs max

STS High to SDO Relinquish Time

150

150

ns max

Load ckt of Figure 4

STS Low to Data Valid (RD = 0)

50

50

ns max

ADC Write Timing

Time

Interval