ICS93776 datasheet(4/8 Pages) ICST

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ICS93776

0793A—03/08/05

Timing Requirements

TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V (unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Operating Clock Frequency

freqop

Input Voltage level: 0-2.50V

340

MHz

Input Clock Duty Cycle

dtin

Clock Stabilization

tSTAB

from VDD = 2.5V to 1% target frequency

100

µs

1. Guaranteed by design, not 100% tested in production.

Switching Characteristics

TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V ± 0.20V (unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

66 MHz to 266 MHz

100

Phase Error

tpe

-150

150

Output to output Skew

Tskew

100

Duty Cycle (Sign Ended)

1,3

66 MHz to 267 MHz

Rise Time, Fall Time

tR , tf

Load=120

Ω/14pF

950

Output Differential Pair

Crossing Voltage

1. Guaranteed by design, not 100% tested in production.

2. Refers to transistion on non-inverting period.

3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies.

This is due to the formular: duty_cycle=twH/tC, where the cycle time (tC)decreases as the frequency increases.

tc-c

Cycle to cycle Jitter

1,2

1.32

VOC

VDD=2.50V

1.23

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