ICS93776 datasheet(1/8 Pages) ICST

Part #	ICS93776

Description	Low Cost DDR Phase Lock Loop Zero Delay Buffer

PDF	8 Pages

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Manufacturer	ICST [Integrated Circuit Systems]

Direct Link	http://www.icst.com

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1 / 8 page

Integrated

Circuit

Systems, Inc.

ICS93776

0793A—03/08/05

Block Diagram

Low Cost DDR Phase Lock Loop Zero Delay Buffer

Pin Configuration

Recommended Application:

DDR Zero Delay Clock Buffer

Product Description/Features:

•

Low skew, low jitter PLL clock driver

•

Max frequency supported = 266MHz (DDR 533)

•I

2C for functional and output control

•

Feedback pins for input to output synchronization

•

Spread Spectrum tolerant inputs

•

3.3V tolerant CLK_INT/C input

Switching Characteristics:

•

CYCLE - CYCLE jitter: <100ps

•

OUTPUT - OUTPUT skew: <100ps

•

DUTY CYCLE: 48% - 52%

ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.

ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.

DDRC0

1

28 GND

DDRT0

2

27 DDRC5

VDD

3

26 DDRT5

DDRT1

4

25 DDRC4

DDRC1

5

24 DDRT4

GND

6

23 VDD

SCLK

7

22 SDATA

CLK_INT

8

21 FB_INC

CLK_INC

9

20 FB_INT

VDDA 10

19 FB_OUTT

GND 11

18 FB_OUTC

VDD 12

17 DDRT3

DDRT2 13

16 DDRC3

DDRC2 14

15 GND

28-Pin 209mil SSOP

Functionality

S

T

U

P

N

IS

T

U

P

T

U

O

e

t

a

t

S

L

P

D

V

AT

N

I

_

K

L

CT

K

L

CC

K

L

CT

T

U

O

_

B

F

V

5

.

2

)

m

o

n

(

LL

H

L

n

o

V

5

.

2

)

m

o

n

(

HH

L

H

n

o

FB_INT

FB_INC

CLK_INT

CLK_INC

SCLK

SD

SDA

AT

TA

A

Control

Logic

FB_OUTT

FB_OUTC

DDRC0

PLL

DDRT0

DDRC1

DDRT1

DDRC2

DDRT2

DDRC3

DDRT3

DDRC4

DDRT4

DDRC5

DDRT5

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