EM6124 datasheet(4/25 Pages) EMMICRO

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EM6124

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1 Bit Interface Description

This 1 bit interface is very simple to use. There are three

modes to load data into the EM6124.

Command byte only mode

To validate this mode, 8 bits must be shifted with bit 3 to

bit 7 set to 1L. This mode is used for blank, set or sleep

mode functions.

Command byte and initialization mode

To validate this mode, 32 bits must be shifted with bit 0

and bit 1 set to 1L. Bit 2 (sleep) can be active or inactive.

Bit 3 to bit 7 (RAM address) can be in any state but it is

important that they are not all simultaneously set to 1L,

otherwise the chip will be in command byte only mode.

Command byte and display information mode

To validate this mode, 128 bits must be shifted, eight first

bits are for command byte, all the other are RAM data

depending of col bit mode and multiplex ratio. There are

also x bits don’t care in each loading depending on the

programming of the chip (see Fig. 4 for more details).

In each RAM’s data loading, the command byte has to be

introduced for the RAM address. Before loading any data

into the RAM the chip has to be initialized.

Command Byte

Command Bits 0 to 7

Blank

Set

Sleep

RAM address

Table 6

Cmdbit 0: Blank bit forces all column outputs off.

Cmdbit 1: Set bit forces all column output on.

Note: If bit 0 and bit 1 are both to 1L, the chip will be in

initialization mode. See remarks below.

Cmdbit 2: Sleep mode bit, stops the voltage booster and the

internal oscillator, active bit col forces all outputs to VSS.

Cmdbits 3-7: RAM address bits. See table 6.

If Cmdbits 3-7 are set to 1L, EM6124 is in Cmd byte only mode.

Initialization Bits

Initialization Bits 8 to 15

Mux Mode

Temp. Coeff.

Checker

Inv.

Checker

Col

Inv.Row

Initialization Bits 16 to 23

M/LSB

Video

Step 1

Step 2

Step 3

Step 4

Step 5

Step 6

Initialization Bits 24 to 31

Icon

Sleep 2 Test 6

Test 5

Test 4

Test 3

Test 2

Fr_ext

Table 7

Mux ratio (Init. bit 8, 9)

mux mode

Table 8

Init.bit 8-9: Mux mode bits. The multiplex ratio is selected by

these two bits. Table 8 shows the corresponding values.

Init.bit 10-11: V

LCD temperature coefficient is selected by these

two bits. Table 11 shows the corresponding values.

Init.bit 12: Checker bit gives the possibility to force all outputs

segments in checked form (see Fig. 10 and Fig. 18.14).

Init.bit 13: Inverse Checker bit gives the possibility to force all

outputs segments in inverse checked form (see Fig. 10 and Fig.

18.15).

Init.bit 14: Col bit configures the EM6124 on row and column

driver or column driver only. In this mode the frame frequency

must be external.

Init.bit 15: Row inversion, possibility to inverse the order of the

row outputs (see Table 10 and Fig. 18.12).

Init.bit 16: M/LSB, possibility to inverse the order loading for

RAM data (see Fig. 4).

Init.bit 17: Video bit, possibility to inverse the content of the

RAM. All the 0L pass to 1L and all the 1L pass to 0L (see Fig.

18.11).

Init.bit 18-23: V

LCD 64 steps programmation bits. See Fig. 8.

Bit 18 (step 1) for MSB and bit 23 (step 6) for LSB.

Init.bit 24: Icon bit adds one line more to the selected mux mode

ratio for icon segments outputs.

Init.bit 25: Sleep 2. Set all outputs at V

SS.

Init.bit 26-30: Must be setted to 0L.

Init.bit 31: Fr_ext give the possibility to supply frame to EM6124

externally. If Fr_ext=1L then FR is input pin and user must

supply signal frame. If Fr_ext=0L then FR is output pin, the

signal frame is internally generated. (

Init.bit 14: has the priority)

Reset 1

Power-up: Must be followed by a RESET cycle. After the

reset 1 pulse the LCD controller driver is set to the

following status:

- All outputs at VSS

- Blank & Set (cmdbits 0,1) = 0L

- Sleep mode (cmdbit 2) = 0L

- RAM address (cmdbits 3 to 7) = 0L

- Multiplex ratio (init.bits 8, 9) = 0L

- Temperature coefficient (init.bits 10,11) = 0L

- Checker & Inv.Checker (init.bits 12, 13) = 0L

- Col Mode (init.bit 14) = 1L

- Inv. Row (init.bit 15) = 0L

- M/LSB (init.bit 16) = 1L

- Video (init.bit 17) = 1L

- VLCD step (init.bits 18 to 23) = 0L

- Icon (init.bit 24) = 0L

- Sleep 2 (init.bit 25) = 1L

- The content of the RAM remains unchanged

- Frame internally generated (init.bit 31) = 0L

An initialization should take place after reset (32 bits

sent).

Pin Assignment

Name

Function

S1..S121

LCD outputs, see Fig.4

AC I/O signal for LCD driver output

Serial data input

Serial data output

CLK

Data clock input

RES1

General reset

RES2

Reset the serial interface counter

VLCD

Internal generated voltage output

VDD1

Power supply for logic

VDD2

Power supply for analogic

VHV

Power supply for high voltage

VSS

Supply GND

Table 9

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