WM8771 datasheet(36/44 Pages) WOLFSON

36 / 44 page

WM8771

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PP Rev 2.0 December 2001

ADCLRC/DACLRC Polarity or DSP Early/Late mode select

LRP

Left Justified / Right Justified /

I2S

0: Standard DACLRC Polarity

1: Inverted DACLRC Polarity

DSP Mode

0: Data in-line with

ADCLRC/DACLRC

1: Data delayed by 1 BCLK

BCP

BITCLK Polarity

0: Normal - DIN[3:0], DACLRC & ADCLRC sampled on

rising edge of BCLK; DOUT changes on falling edge of

BCLK.

1: Inverted - DIN[3:0], DACLRC & ADCLRC sampled on

falling edge of BCLK; DOUT changes on rising edge of

BCLK.

5:4

WL[1:0]

Input Word Length

00: 16-bit Mode

01: 20-bit Mode

10: 24-bit Mode

11: 32-bit Mode (not supported in right justified mode)

ADCHPD

ADC Highpass Filter Disable:

0: Highpass Filter enabled

1: Highpass Filter disabled

2:0

ADCRATE[2:0]

010

Master Mode MCLK:ADCLRC ratio select:

000: 128fs

001: 192fs

010: 256fs

011: 384fs

100: 512fs

ADCOSR

ADC oversample rate select

0: 128x oversampling

1: 64x oversapmling

6:4

DACRATE[2:0]

010

Master Mode MCLK:DACLRC ratio select:

000: 128fs

001: 192fs

010: 256fs

011: 384fs

100: 512fs

10111

Master Mode

control

Maser/Slave interface mode select

0: Slave Mode – ADCLRC, DACLRC and BCLK are inputs

1: Master Mode – ADCLRC, DACLRC and BCLK are outputs

PWDN

Chip Powerdown Control (works in tandem with ADCD and

DACD):

ADCD

ADC powerdown:

11000

Powerdown

Control

5:2

DACD[3:0]

1111

DAC powerdown

4:0

LAG[4:0]

01100

Attenuation data for left channel ADC gain in 1dB steps

MUTE

Mute for Left channel ADC:

0: Mute off

1: Mute on

11001

Attenuation

ADCL

LRBOTH

Setting LRBOTH will write the same gain value to LAG[4:0 and

RAG[4:0]

WM8771 Datasheet(PDF) 36 Page - Wolfson Microelectronics plc

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