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WM8771 Datasheet(PDF) 15 Page - Wolfson Microelectronics plc

Part # WM8771
Description  24-bit, 192kHz 8-Channel Codec
PDF  44 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8771 Datasheet(HTML) 15 Page - Wolfson Microelectronics plc

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WM8771
w
PP Rev 2.0 December 2001
15
System Clock Frequency (MHz)
128fs
192fs
256fs
384fs
512fs
768fs
SAMPLING
RATE
(DACLRC/
ADCLRC)
ADCRATE/
DACRATE
=000
ADCRATE/
DACRATE
=001
ADCRATE/
DACRATE
=010
ADCRATE/
DACRATE
=011
ADCRATE/
DACRATE
=100
ADCRATE/
DACRATE
=101
32kHz
4.096
6.144
8.192
12.288
16.384
24.576
44.1kHz
5.6448
8.467
11.2896
16.9340
22.5792
33.8688
48kHz
6.114
9.216
12.288
18.432
24.576
36.864
96kHz
12.288
18.432
24.576
36.864
Unavailable
Unavailable
192kHz
24.576
36.864
Unavailable
Unavailable
Unavailable
Unavailable
Table 8 Master Mode ADC/DACLRC frequency selection
BCLK is also generated by the WM8771. The frequency of BCLK depends on the mode of operation.
In 128/192fs modes (ADCRATE/DACRATE=000 or 001) BCLK = MCLK/2. In 256/384/512fs modes
(ADCRATE/DACRATE=010 or 011 or 100) BCLK = MCLK/4. However if DSP mode is selected as
the audio interface mode then BCLK=MCLK. This is to ensure that there are sufficient BCLKs to
clock in all eight channels. Note that DSP mode cannot be used in 128fs mode for word lengths
greater than 16 bits or in 192fs mode for word lengths greater than 24 bits.
ZERO DETECT
The WM8770 has a zero detect circuit for each DAC channel which detects when 1024 consecutive
zero samples have been input. Two zero flag outputs (ZFLAG1 and ZFLAG2) may be programmed to
output the zero detect signals (see Table 9) which may then be used to control external muting
circuits. A ‘1’ on ZFLAG1 or ZFLAG2 indicates a zero detect. The zero detect may also be used to
automatically enable the PGA mute by setting IZD. The zero flag output may be disabled by setting
DZFM to 0000. The zero flag signal for a DAC channel will only be enabled if that channel is enabled
as an input to the output summing stage.
DZFM[3:0]
ZFLAG1
ZFLAG2
0000
Zero flag disabled
Zero flag disabled
0001
All channels zero
All channels zero
0010
Left channels zero
Right channels zero
0011
Channel 1 zero
Channels 2-4 zero
0100
Channel 1 zero
Channel 2 zero
0101
Channel 1 zero
Channel 3 zero
0110
Channel 1 zero
Channel 4 zero
0111
Channel 2 zero
Channel 3 zero
1000
Channel 2 zero
Channel 4 zero
1001
Channel 3 zero
Channel 4 zero
1010
Channels 1-3 zero
Channel 4 zero
1011
Channel 1 zero
Channels 2 & 3 zero
1100
Channel 1 left zero
Channel 1 right zero
1101
Channel 2 left zero
Channel 2 right zero
1110
Channel 3 left zero
Channel 3 right zero
1111
Channel 4 left zero
Channel 4 right zero
Table 9 Zero Flag Output Select



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