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B9948
Document #: 38-07079 Rev. *D
Page 2 of 6
Note:
1.
PD = internal pull-down, PU = internal pull-up.
Output Enable/ Disable
The B9948 features a control input to enable or disable the
outputs. This data is latched on the falling edge of the input
clock. When SYNC_OE is asserted LOW, the outputs are dis-
abled in a LOW state. When SYNC_OE is set HIGH, the out-
puts are enabled as shown in Figure 1.
Pin Description[[1]]
Pin
Name
PWR
I/O
Description
3
PECL_CLK
I, PU
PECL Input Clock
4
PECL_CLK#
I, PD
PECL Input Clock
2
TCLK
I, PU
External Reference/Test Clock Input
9, 11, 13, 15, 17, 19,
21, 23, 25, 27, 29,
31
Q(11:0)
VDDC
O
Clock Outputs
1
TCLK_SEL
I, PU
Clock Select Input. When LOW, PECL clock is selected and
when HIGH TCLK is selected.
5
SYNC_OE
I, PU
Output Enable Input. When asserted HIGH, the outputs are
enabled and when set LOW the outputs are disabled in a LOW
state.
6
TS#
I, PU
Three-state Control Input. When asserted LOW, the output
buffers are three-stated. When set HIGH, the output buffers
are enabled.
10, 14, 18, 22, 26,
30
VDDC
3.3V Power Supply for Output Clock Buffers
7
VDD
3.3V Power Supply
8, 12, 16, 20, 24,
28, 32
VSS
Common Ground
TCLK
SYNC_OE
Q
Figure 1. SYNC_OE Timing Diagram
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