SG5701DP datasheet(9/13 Pages) TGS

9 / 13 page

Product Specification

Low Cost Green-Mode PWM Controller for Flyback Converters

SG5701

- 9 -

www.sg.com.tw

Version 1.0(IAO33.0025.B1)

Mar. 28, 2006

Under Voltage Lockout (UVLO)

The turn-on and turn-off thresholds of the SG5701

are fixed internally at 16.3V/11.7V. During start-up, the

hold-up capacitor must be charged to 16.3V through the

start-up resistor, so that the SG5701 will be enabled. The

hold-up capacitor will continue to supply VDD until power

can be delivered from the auxiliary winding of the main

transformer. VDD must not drop below 11.7V during this

start-up process. This UVLO hysteresis window ensures

that hold-up capacitor will be adequate to supply VDD

during start-up.

Gate Output

The SG5701 BiCMOS output stage is a fast totem

pole gate driver. Cross conduction has been avoided to

minimize heat dissipation, increase efficiency, and

enhance reliability. The output driver is clamped by an

internal 17V Zener diode in order to protect power

MOSFET transistors against undesired over-voltage gate

signals.

Built-in Slope Compensation

The sensed voltage across the current sense resistor

is used for current mode control and pulse-by-pulse

current limiting. Built-in slope compensation will

improve stability and prevent sub-harmonic oscillations

due to peak-current mode control. The SG5701 has a

synchronized, positively-sloped ramp built-in at each

switching cycle. The slope of the ramp is:

(max)

Duty

Noise Immunity

Noise from the current sense or the control signal can

cause significant pulse width jitter, particularly in

continuous-conduction mode. While slope compensation

helps alleviate these problems, further precautions should

still be taken. Good placement and layout practices should

be followed. Avoiding long PCB traces and component

leads, locating compensation and filter components near

the SG5701, and increasing the power MOS gate

resistance is advised.

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