DS3252 datasheet(13/71 Pages) DALLAS

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Table 6-E. Parallel Bus Mode Pin Descriptions

Note: These pins are active in parallel bus mode.

NAME

TYPE

FUNCTION

MOT

Motorola-Style Parallel CPU Interface

0 = Parallel CPU interface is Intel-style

1 = Parallel CPU interface is Motorola-style

ALE

Address Latch Enable. This signal controls a latch on the A[3:0] inputs. For a nonmultiplexed parallel

CPU interface, ALE is wired high to make the latch transparent. For a multiplexed parallel CPU

interface, the falling edge of ALE latches the address.

Chip Select (Active Low).

CS must be asserted to read or write internal registers.

WR / R/W

Write Enable (Active Low) or Read/Write Select. For the Intel-style parallel CPU interface (MOT =

0),

WR is asserted to write internal registers. For the Motorola-style parallel CPU interface (MOT = 1),

W determines the type of bus transaction, with R/W = 1 indicating a read and R/W = 0 indicating a

write.

RD / DS

Read Enable (Active Low) or Data Strobe (Active Low). For the Intel-style parallel CPU interface

(MOT = 0),

RD is asserted to read internal registers. For the Motorola-style parallel CPU interface

(MOT = 1), the rising edge of

DS writes data to internal registers.

A[5:0]

Address Bus. These inputs specify the address of the internal register to be accessed. A5 is not

present on the DS3252. A5 and A4 are not present on the DS3251.

D[7:0]

I/O

Data Bus. These bidirectional lines are inputs during writes to internal registers and outputs during

reads.

INT

Interrupt Output (Active Low, Open Drain). This pin is forced low in response to one or more

unmasked, active interrupt sources within the device.

INT remains low until the interrupt is serviced or

masked.

Table 6-F. SPI Bus Mode Pin Descriptions

Note: These pins are active in SPI bus mode.

NAME

TYPE

FUNCTION

MOT

RD, WR

Wire these pins low to enable SPI bus mode.

Chip Select (Active Low).

CS must be asserted to read or write internal registers.

SCLK

Serial Clock for SPI Interface. SCLK is always driven by the SPI bus master.

SDI

Serial Data Input for SPI Interface. The SPI bus master transmits data to the device on this pin.

SDO

Serial Data Output for SPI Interface

The device transmits data to the SPI bus master on this pin.

CPHA

SPI Clock Phase

0 = data is latched on the leading edge of the SCLK pulse

1 = data is latched on the trailing edge of the SCLK pulse

CPOL

SPI Clock Polarity

0 = SCLK is normally low and pulses high during bus transactions

1 = SCLK is normally high and pulses low during bus transactions

INT

Interrupt Output (Active Low, Open Drain). This pin is forced low in response to one or more

unmasked, active interrupt sources within the device.

INT remains low until the interrupt is serviced or

masked.

Note 1: PIN TYPES

I = input pin

IPU = input pin with internal 10k

W pullup

O = output pin

O3 = output pin that can be tri-stated

P = power-supply pin

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