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DS640PP4

CS44L11

6. APPLICATIONS

6.1

Grounding and Power Supply Decoupling

As with any switching converter, the CS44L11 requires careful attention to power supply and grounding ar-

rangements to optimize performance. Figures 3 and 4 show the recommended power arrangement with VD

and VA_HPx connected to clean supplies. Decoupling capacitors should be located as close to the device

package as possible. If desired, all supply pins may be connected to the same supply, but a decoupling ca-

pacitor should still be used on each supply pin.

6.2

Clock Modes

One of the characteristics of a PWM amplifier is that the frequency content of out-of-band noise generated

by the modulator is dependent on the PWM switching frequency. The systems designer will specify the ex-

ternal filter based on this switching frequency. The obvious implementation in a digital PWM system is to

directly lock the PWM switching rate to the incoming data sample rate. However, this would require a tun-

able filter to attenuate the switching frequency across the range of possible sample rates. To simplify the

external filter design and to accommodate sample rates ranging from 8 kHz to 96 kHz the CS44L11 Con-

troller uses several clock modes that keep the PWM switching frequency in a small range.

In Control Port Mode, for operation at a particular sample rate the user selects register settings (refer to

Section 4.9 and Tables 11 and 13) based on their MCLK and MCLK/LRCK parameters. When using

Stand-Alone mode, refer to Tables Tables 12 and 14 for available clock modes.

6.3

De-Emphasis

The CS44L11 includes on-chip digital de-emphasis. Figure 6 shows the de-emphasis curve. The frequency

response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs.

The de-emphasis feature is included to accommodate older audio recordings that utilize pre-emphasis

equalization as a means of noise reduction.

6.4

PWM PopGuard Transient Control

power-down. This technique minimizes the audio transients commonly produced by a single-ended, sin-

gle-supply converter when it is implemented with external DC-blocking capacitors connected in series with

the audio outputs.

When the device is initially powered-up, the HP_x outputs are clamped to GND. Following a delay each out-

put begins to increase the PWM duty cycle toward the quiescent voltage point. By a speed set by the

RMP_SP bit, the HP_x outputs will later reach the bias point (50% PWM duty cycle), and audio output be-

gins. This gradual voltage ramping allows time for the external DC-blocking capacitor to charge to the qui-

escent voltage, minimizing the power-up transient.

To prevent transients at power-down, the device must first enter its power-down state. When this occurs,

audio output ceases and the PWM duty cycle is decreased until the HP_x outputs reach GND. The time

required to reach GND is determined by the RMP_SP bits. This allows the DC-blocking capacitors to slowly

discharge. Once this charge is dissipated, the power to the device may be turned off, and the system is

ready for the next power-on.

To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge before

turning off the power or exiting the power-down state. If full discharge does not occur, a transient will occur

when the audio outputs are initially clamped to GND. The time that the device must remain in the pow-

er-down state is related to the value of the DC-blocking capacitance and the output load. For example, with