CS42448 datasheet(68/70 Pages) CIRRUS

68 / 70 page

DS648PP2

14 REVISION HISTORY

Revision

Date

Changes

July 2004

Initial Release

October 2004

Corrected I²C Address in section 4.7.2 on page 39.

Corrected Chip I.D. in section 6.2.1 on page 44.

PP1

January 2005

Initial Preliminary Product (PP) Release subject to legal notice below.

Added pin numbers to “Typical Connection Diagram” on page 10.

Changed ADC TDM, Double-Speed Mode parameters. See Note 2 on page 11

and Note 18 on page 21.

Added ADC3 MUX Interchannel Isolation characteristic in section “Character-

istics and Specifications” beginning on page 11.

Changed SCLK Falling Edge to ADC_SDOUT Output Valid (tdpd) maximum

specification to 35 ns in section “Characteristics and Specifications” beginning

on page 11.

Changed ADC Passband Ripple maximum specifications for SSM, DSM &

QSM in section “Characteristics and Specifications” beginning on page 11.

Changed DAC Frequency Response specifications for SSM, DSM & QSM in

section “Characteristics and Specifications” beginning on page 11.

Changed ADC Quad-Speed Mode parameters. See Note 19 on page 21.

Added section “De-Emphasis Filter” on page 31.

Added SCLK/LRCK & MCLK/LRCK ratio parameters in Tables 5 - 8 on page

33.

Corrected section “TDM” on page 35.

Changed AIN1-6 Volume Control range from (+12 dB to -115.5 dB) to (+24 dB

to -64 dB) in register “AINx Volume Control (AINx_VOL[7:0])” on page 53.

Removed the “Error Mode (MODE[1:0])” control bits from register “Status Con-

trol (address 18h)” on page 54. See “Interrupt Pin Control (INT[1:0])” on

page 54, “ADC CLOCK ERROR (ADC_CLK Error)” on page 54 and “ADC

Overflow (ADCX_OVFL)” on page 55 for the Active Mode setting.

PP2

February 2005

Corrected Figures 27-29.

Added section “Ordering Information” on page 67.

Table 16. Revision History

CS42448 Datasheet(PDF) 68 Page - Cirrus Logic