CY29772AI datasheet(7/12 Pages) CYPRESS

7 / 12 page

CY29772

Document #: 38-07572 Rev. *A

Page 7 of 12

tJIT(CC)

Cycle-to-Cycle Jitter

Same frequency (125 MHz)

RMS (1

σ)

–7

Same frequency

–

150

Multiple frequencies

–

435

tJIT(PER)

Period Jitter

Same frequency (125 MHz)

RMS (1

σ)

–6

Same frequency

–

Multiple frequencies

–

235

tJIT(φ)

I/O Phase Jitter

–

150

tLOCK

Maximum PLL Lock Time

–

AC Parameters (VDD = 3.3V ± 5%, TA = –40°C to +85°C) [6]

Parameter

Description

Condition

Min.

Typ.

Max.

Unit

fVCO

VCO Frequency

200

–

500

MHz

fXTAL

Crystal Frequency Range

See Table 7

–

MHz

fin

Input Frequency

÷4 Feedback

–

125

MHz

÷6 Feedback

33.3

–

83.3

÷8 Feedback

–

62.5

÷10 Feedback

–

÷12 Feedback

16.6

–

41.6

÷16 Feedback

12.5

–

31.25

÷20 Feedback

–

÷24 Feedback

8.3

–

20.8

÷32 Feedback

6.25

–

15.625

÷40 Feedback

–

12.5

Bypass mode (PLL_EN = 0)

–

200

frefDC

Input Duty Cycle

–

tr, tf

TCLK Input Rise/FallTime

0.8V to 2.0V

–

1.0

fMAX

Maximum Output Frequency

÷2 Output

100

–

200

MHz

÷4 Output

–

125

÷6 Output

33.3

–

83.3

÷8 Output

–

62.5

÷10 Output

–

fMAX

Maximum Output Frequency

(continued)

÷12 Output

16.6

–

41.6

MHz

÷16 Output

12.5

–

31.25

÷20 Output

–

÷24 Output

8.3

–

20.8

fSCLK

Serial Clock Frequency

–

MHz

Output Duty Cycle

fMAX < 100 MHz

–

fMAX > 100 MHz

–

tr, tf

Output Rise/Fall times

0.55V to 2.4V

0.1

–

1.0

t(φ)

Propagation Delay (static phase

offset)

TCLK to FB_IN, same VDD

–125

–

125

tsk(O)

Output-to-Output Skew

Skew within Bank A

–

Skew within Bank B

–

100

AC Electrical Specifications (VDD = 2.5V ± 5%, TA = –40°C to +85°C) (continued)[6]

Parameter

Description

Condition

Min.

Typ.

Max.

Unit

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