7

Parameter

Symbol

Typ.

Units

Test Conditions

Fig.

Note

Resistance (Input-Output)

R

I-O

Ω

V

3, 13

Capacitance (Input-Output)

C

I-O

1.7

pF

f = 1 MHz

3, 13

Input-Input Insulation

I

I-I

0.5

nA

45% Relative Humidity,

11

Leakage Current

V

Resistance (Input-Input)

R

I-I

Ω

V

I-I

= 500 Vdc

11

Capacitance (Input-Input)

C

I-I

0.55

pF

f = 1 MHz

11

Propagation Delay Time of Enable

t

ELH

35

ns

6, 7

3, 7

from V

EH

to V

EL

R

Propagation Delay Time of Enable

t

EHL

35

ns

I

I

= 13 mA, V

EH

= 3 V, V

EL

= 0 V

6, 7

3, 8

from V

EL

to V

EH

Output Rise Time (10-90%)

t

r

30

ns

3

R

Output Fall Time (90-10%)

t

f

24

ns

3

Input Capacitance

C

I

60

pF

f = 1 MHz, V

3

PINS 1 to 2 or 5 to 6

Typical Specifications

T

Notes:

1. Bypassing of the power supply line is required, with a 0.1

µF ceramic disc capacitor adjacent to each isolator. The power supply bus

for the isolators should be separate from the bus for any active loads, otherwise additional bypass capacitance may be needed to

suppress regenerative feedback via the power supply.

2. Derate linearly at 1.2 mA/

°C above T

A

= 100

°C.

3. Each channel.

4. Device considered a two terminal device: pins 1 through 8 are shorted together, and pins 9 through 16 are shorted together.

5. The t

PLH

propagation delay is measured form the 6.5 mA point on the trailing edge of the input pulse to the 1.5 V point on the trailing

edge of the output pulse.

6. The t

PHL

propagation delay is measured from the 6.5 mA point on the leading edge of the input pulse to the 1.5 V point on the leading

edge of the output pulse.

7. The t

ELH

enable propagation delay is measured from the 1.5 V point on the trailing edge of the enable input pulse to the 1.5 V point

on the trailing edge of the output pulse.

8. The t

EHL

enable propagation delay is measured from the 1.5 V point on the leading edge of the enable input pulse to the 1.5 V point

on the leading edge of the output pulse.

9. CM

H

is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state, i.e.

V

OUT

> 2.0 V.

10. CM

L

is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state, i.e.

V

OUT

< 0.8 V.

11. Measured between adjacent input leads shorted together, i.e. between 1, 2 and 4 shorted together and pins 5, 6 and 8 shorted

together.

12. No external pull up is required for a high logic state on the enable input.

13. Measured between pins 1 and 2 or 5 and 6 shorted together, and pins 10 through 15 shorted together.

14. Parameters shall be tested as part of device initial characterization and after process changes. Parameters shall be guaranteed to the

limits specified for all lots not specifically tested.

15. Standard parts receive 100% testing at 25

°C (Subgroups 1 and 9). Hi-Rel and SMD parts receive 100% testing at 25, 125, and -55°C

(Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).