7534 datasheet(28/55 Pages) RENESAS

28 / 55 page

7534 Group

Rev.2.00

Jun 21, 2004

page 28 of 54

REJ03B0099-0200Z

Fig. 31 Structure of serial I/O1-related registers (5)

UART control register

(UARTCON: address 001B16)

Character length selection bit

0: 8 bits

1: 7 bits

Parity enable bit

0: Parity checking disabled

1: Parity checking enabled

Parity selection bit

0: Even parity

1: Odd parity

Stop bit length selection bit

0: 1 stop bit

1: 2 stop bits

P-channel output disable bit

0: CMOS output

1: N-channel open-drain output

Not used (returns “1” when read)

CPU read: Disabled

CPU write: Set/Clear

Hardware read: Used

Hardware write: Not used

Serial I/O1 control register

(SIO1CON: address 001A16)

BRG count source selection bit

0: f(XIN)

1: f(XIN)/4

Not used (returns “1” when read)

Continuous transmit valid bit

0: Continuous transmit invalid

1: Continuous transmit valid

Transmit interrupt source selection bit

0: Interrupt when transmit buffer has

emptied

1: Interrupt when transmit shift

operation is completed

Transmit enable bit

0: Transmit disabled

1: Transmit enabled

Receive enable bit

0: Receive disabled

1: Receive enabled

Serial I/O1 mode selection bits

00: I/O port

01: Not available

10: UART mode

11: USB mode

CPU read: Disabled

CPU write: Set/Clear

Hardware read: Used

Hardware write: Not used

CPU read: Disabled

CPU write: Set/Clear

Hardware read: Used

Hardware write: Not used

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