6

DLP2010LC

DLPS180 – MAY 2020

www.ti.com

Product Folder Links: DLP2010LC

Submit Documentation Feedback

Copyright © 2020, Texas Instruments Incorporated

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device is not implied at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure above or below the Recommended Operating Conditions for extended periods may affect device

reliability.

(2)

All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD:

VSS, VDD, VDDI, VOFFSET, VBIAS, and VRESET.

(3)

VOFFSET supply transients must fall within specified voltages.

(4)

Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw.

(5)

Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current

draw.

(6)

Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw.

(7)

This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential

inputs must not exceed the specified limit or damage may result to the internal termination resistors.

(8)

The highest temperature of the active array (as calculated by the Micromirror Array Temperature Calculation), or of any point along the

Window Edge as defined in Figure 19. The locations of thermal test points TP2 and TP3 in Figure 19 are intended to measure the

highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature,

that point should be used.

(9)

Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in

Figure 19. The window test points TP2 and TP3 shown in Figure 19 are intended to result in the worst case delta. If a particular

application causes another point on the window edge to result in a larger delta temperature, that point should be used.

6 Specifications

6.1 Absolute Maximum Ratings

See

(1)

MIN

MAX

UBIT

Supply voltage

VDD

Supply voltage for LPSDR low speed interface

–0.5

2.3

V

VDDI

–0.5

2.3

VOFFSET

–0.5

10.6

VBIAS

–0.5

19

VRESET

–15

0.5

| VDDI–VDD |

0.3

| VBIAS–VOFFSET |

11

| VBIAS–VRESET |

34

Input voltage

–0.5

VDD + 0.5

V

–0.5

VDDI + 0.5

Input pins

| VID |

810

mV

IID

SubLVDS input differential current

8.1

mA

Clock frequency

Clock frequency for low speed interface LS_CLK

130

MHz

Clock frequency for high speed interface DCLK

620

Environmental

–20

90

°C

–40

90

Dew Point Temperature - operating and non-operating

(non-condensing)

81

Absolute Temperature delta between any point on the

30

(1)

The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

(2)

Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative

6.2 Storage Conditions

applicable for the DMD as a component or non-operational in a system

MIN

MAX

UNIT

DMD storage temperature

–40

85

°C

24

°C

28

36

°C

Cumulative time in elevated dew point temperature range

6

Months