VT8371
Preliminary Revision 1.02, January 7, 2000
-2-
Features
7HFKQRORJLHV ,QF
'HOLYHULQJ 9DOXH
'HOLYHULQJ 9DOXH
• Full Featured Accelerated Graphics Port (AGP) Controller
− Synchronous and pseudo-synchronous with the host CPU bus with optimal skew control
PCI
AGP
CPU
Mode
33 MHz
66 MHz
100 MHz DDR
3x synchronous
− AGP v2.0 compliant
− Supports SideBand Addressing (SBA) mode (non-multiplexed address / data)
− Supports 66 MHz 1x, 2x and 4x modes for AD and SBA signaling
− Pipelined split-transaction long-burst transfers up to 1GB/sec
− Thirty-two level read request queue
− Four level posted-write request queue
− Thirty-two level (quadwords) read data FIFO (256 bytes)
− Sixteen level (quadwords) write data FIFO (128 bytes)
− Intelligent request reordering for maximum AGP bus utilization
− Supports Flush/Fence commands
− Graphics Address Relocation Table (GART)
− One level TLB structure
− Sixteen entry fully associative page table
− LRU replacement scheme
− Windows 95 OSR-2 VXD and integrated Windows 98 / Windows 2000 miniport driver support
• Concurrent PCI Bus Controller
− PCI buses are synchronous / pseudo-synchronous to host CPU bus
− 33 MHz operation on the primary PCI bus
− 66 MHz PCI operation on the AGP bus
− PCI-to-PCI bridge configuration on the 66MHz PCI bus
− Supports up to five PCI masters
− Peer concurrency
− Concurrent multiple PCI master transactions; i.e., allow PCI masters from both PCI buses active at the same time
− Zero wait state PCI master and slave burst transfer rate
− PCI to system memory data streaming up to 132Mbyte/sec
− Two lines (32 double-words) of CPU to PCI posted write buffers
− Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting possibilities
− Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
− Thirty-two levels (double-words) of post write buffers from PCI masters to DRAM
(two cache lines / 16 double-words for PCI bus, two cache lines / 16 double-words for Athlon processor interface)
− Sixteen levels (double-words) of prefetch buffers from DRAM for access by PCI masters
− Delay transaction from PCI master accessing DRAM
− Read caching for PCI master reading DRAM
− Transaction timer for fair arbitration between PCI masters (granularity of two PCI clocks)
− Symmetric arbitration between Host/PCI bus for optimized system performance
− Complete steerable PCI interrupts
− PCI-2.2 compliant, 32 bit 3.3V PCI interface with 5V tolerant inputs
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
