XRT7250 datasheet(180/463 Pages) EXAR

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DS3/E3 FRAMER IC

XRT7250

REV. 1.1.1

161

1. Write the 6-bit FEAC code (to be sent) into the Tx

DS3 FEAC Register.

2. Enable the Transmit FEAC Processor.

3. Initiate the Transmission of the FEAC Message.

Each of these steps will be described in detail below.

STEP 1 - Writing in the six bit FEAC Codeword (to

be sent)

In this step, the µP/µC writes the six bit FEAC code

word into the Tx DS3 FEAC Register. The bit format

of this register is presented below.

STEP 2 - Enabling the Transmit FEAC Processor

In order to enable the Transmit FEAC Processor

(within the Transmit DS3 HDLC Controller block) the

user must write a 1 into bit 2 (Tx FEAC Enable) within

the Tx DS3 FEAC Configuration and Status Register,

as depicted below.

At this point, the Transmit FEAC Processor can be

commanded to begin transmission (See STEP 3).

STEP 3 - Initiate the Transmission of the FEAC

Message

The user can initiate the transmission of the FEAC

code word (residing in the Tx DS3 FEAC register) by

writing a 1 to bit 1 (Tx FEAC Go) within the Tx DS3

FEAC Configuration and Status register, as depicted

below.

NOTE: While executing this particular write operation, the

user should write the binary value 000xx110b into the Tx

DS3 FEAC Configuration and Status Register. By doing

this the user insures that a 1 is also being written to Bit 2

(Tx FEAC Enable) of the register, in order to keep the

Transmit FEAC Processor enabled.

Once this step has been completed, the Transmit

FEAC Processor will proceed to transmit the 16 bit

FEAC code via the outbound DS3 frames. This 16 bit

FEAC message will be transmitted repeatedly 10

consecutive times. Hence, this process will require a

total of 160 DS3 Frames. During this process the Tx

FEAC Busy bit (Bit 0, within the Transmit DS3 FEAC

Configuration and Status register) will be asserted,

indicating that the Tx FEAC Processor is currently

transmitting the FEAC Message to the remote Termi-

nal. This bit-field will toggle to "0" upon completion of

the 10th transmission of the FEAC Code Message.

The Transmit FEAC Processor will generate an inter-

rupt (if enabled) to the local µP/µC, upon completion

of the 10th transmission of the FEAC Message. The

purpose of having the Framer IC generating this inter-

rupt is to let the local µP/µC know that the Transmit

FEAC Processor is now available and ready to trans-

mit a new FEAC message. Finally, once the Transmit

FEAC Processor has completed its 10th transmission

of a FEAC Code Message it will then begin sending

TX DS3 FEAC REGISTER (ADDRESS = 0X32)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT2

BIT 1BIT 0

Not Used

TxFEAC[5]

TxFEAC[4]

TxFEAC[3]

TxFEAC[2]

TxFEAC[1]

TxFEAC[0]

Not Used

R/W

TRANSMIT DS3 FEAC CONFIGURATION AND STATUS REGISTER (ADDRESS = 0X31)

BIT 7BIT 6BIT 5BIT 4BIT 3

BIT2BIT 1BIT 0

Not Used

TxFEAC

Interrupt

Enable

TxFEAC

Interrupt

Status

TxFEAC

Enable

TxFEAC

Busy

R/W

xxxx

TRANSMIT DS3 FEAC CONFIGURATION AND STATUS REGISTER (ADDRESS = 0X31)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT2

BIT 1BIT 0

Not Used

TxFEAC

Interrupt

Enable

TxFEAC

Interrupt

Status

TxFEAC

Enable

TxFEAC

Busy

R/W

xxxx

XRT7250 Datasheet(PDF) 180 Page - Exar Corporation

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