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XRT7250 Datasheet(PDF) 251 Page - Exar Corporation |
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XRT7250 Datasheet(HTML) 251 Page - Exar Corporation |
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251 / 463 page  XRT7250 DS3/E3 FRAMER IC áç áç áç áç REV. 1.1.1 232 Setting this bit-field to “1” enables this interrupt. Con- versely, setting this bit-field to “0” disables this inter- rupt. Servicing the Receive FEAC Message - Validation Interrupt. Whenever the XRT7250 Framer IC generates this in- terrupt, it will do the following. • It will assert the Interrupt Request output pin (INT) by driving it "Low". • It will set Bit 2 (RxFEAC Remove Interrupt Status), within the RxDS3 FEAC Interrupt Enable/Status Register to “1”, as indicated below. • It will write the delete contents of the most recently validated FEAC Message from the Rx DS3 FEAC Register, as indicated below. 4.3.6.2.11 The Completion of Reception of a LAPD Message Interrupt If the Completion of Reception of a LAPD Message interrupt is enabled, then the XRT7250 Framer IC will generate an interrupt anytime the Receive HDLC Controller block has received a new LAPD Message buffer, from the Remote Terminal Equipment, and has stored the contents of this message in the Receive LAPD Message Buffer. Enabling/Disable the Receive LAPD Message In- terrupt The user can enable or disable the Receive LAPD Message Interrupt by writing the appropriate data into RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0 Not Used FEAC Valid RxFEAC Remove Interrupt Enable RxFEAC Remove Interrupt Status RxFEAC Valid Interrupt Enable RxFEAC Valid Interrupt Status RO RO RO RO R/W RUR R/W RUR 00 00 X 0 X 0 RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0 Not Used FEAC Valid RxFEAC Remove Interrupt Enable RxFEAC Remove Interrupt Status RxFEAC Valid Interrupt Enable RxFEAC Valid Interrupt Status RO RO RO RO R/W RUR R/W RUR 00 000 011 RXDS3 FEAC REGISTER (ADDRESS = 0X16) BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0 Not Used RxFEAC[5:0] Not Used RO RO RO RO R/O R/O R/O R/O 0 X XXXX X 0 |
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