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XRT7250 Datasheet(PDF) 249 Page - Exar Corporation |
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XRT7250 Datasheet(HTML) 249 Page - Exar Corporation |
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249 / 463 page  XRT7250 DS3/E3 FRAMER IC áç áç áç áç REV. 1.1.1 230 4.3.6.2.8 The Detection of CP-Bit Error Inter- rupt If the Detection of CP-Bit Error Interrupt is enabled, then the XRT7250 Framer IC will generate an inter- rupt, anytime the Receive DS3 Framer block has de- tected a CP-bit error, within the incoming DS3 data stream. Enabling and Disabling the Detection of CP-Bit Error Interrupt: The user can enable or disable the Detection of CP- Bit Error Interrupt, by writing the appropriate value in- to Bit 7 (CP-Bit Error Interrupt Enable) within the RxDS3 Interrupt Enable Register, as illustrated below. Setting this bit-field to “1” enables this interrupt. Con- versely, setting this bit-field to “0” disables this inter- rupt. Servicing the Detection of CP-Bit Error Interrupt Whenever the XRT7250 Framer IC detects this inter- rupt, it will do all of the following. • It will assert the Interrupt Request output pin (INT) by driving it "High". • It will set Bit 7 (CP-Bit Error Interrupt Status) within the Rx DS3 Interrupt Status Register, to “1”, as indi- cated below. Whenever the Terminal Equipment encounters the Detection of CP-bit Error Interrupt, it should do the following. • It should read contents of PMON Frame CP-Bit Error Count Register (located at 0x72 and 0x73), in order to determine the number of CP-bit errors recently received. 4.3.6.2.9 The Receive FEAC Message - Valida- tion Interrupt If the Receive FEAC Message - Validation Interrupt is enabled, then the XRT7250 Framer IC will generate an interrupt any time the Receive FEAC Processor validates a new FEAC (Far-End Alarm & Control) Message. In particular, the Receive FEAC Processor will vali- date a FEAC Message, it that same FEAC Message has been received in 8 of the last 10 FEAC Message receptions. Enabling/Disabling the Receive FEAC Message - Validation Interrupt The user can enable or disable the Receive FEAC Message - Validation Interrupt, by writing the appro- priate data into Bit 1 (RxFEAC Valid Interrupt Enable) within the RxDS3 FEAC Interrupt Enable/Status Reg- ister, as indicated below. RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0 CP Bit Error Interrupt Enable LOS Interrupt Enable AIS Interrupt Enable Idle Interrupt Enable FERF Interrupt Enable AIC Interrupt Enable OOF Interrupt Enable P-Bit Error Interrupt Enable R/W R/W R/W R/W R/W R/W R/W R/W 00 000 000 RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0 CP-Bit Error Interrupt Status LOS Interrupt Status AIS Interrupt Status Idle Interrupt Status FERF Interrupt Status AIC Interrupt Status OOF Interrupt Status P-Bit Error Interrupt Status RURRUR RUR RUR RURRUR RURRUR 10 000 001 |
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