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XRT7250 Datasheet(PDF) 266 Page - Exar Corporation |
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XRT7250 Datasheet(HTML) 266 Page - Exar Corporation |
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266 / 463 page ![]() áç áç áç áç XRT7250 DS3/E3 FRAMER IC REV. 1.1.1 247 indicate that it is processing the last nibble, within a given E3 frame, by pulsing its TxNibFrame output pin "High" for one TxNibClk clock period. When the Ter- minal Equipment detects a pulse at its Tx_Start_of_Frame input pin, it is expected to trans- mit the first nibble, of the very next outbound E3 frame to the XRT7250 via the E3_Data_Out[3:0] (or TxNib[3:0] pins). Finally, for the Nibble-Parallel Mode operation, the XRT7250 will pulse the TxOHInd output pin "High” for 3 nibble-periods (e.g., the 3 nibbles consisting of the 10 bit FAS pattern, the “A” and the “N” bits). The Tx- OHInd output pin will remain "Low” for the remainder of the frame period. The TxOHInd output pin will tog- gle "High” one-nibble period before the Transmit Sec- tion (of the Framer IC) processes the first four bits of the FAS pattern. The behavior of the signals between the XRT7250 and the Terminal Equipment for E3 Mode 4 Operation is illustrated in Figure 107. How to configure the XRT7250 into Mode 4 1. Set the NibIntf input pin "High". 2. Set the TimRefSel[1:0] bit-fields (within the Framer Operating Mode Register) to "00" as illus- trated below. FIGURE 107. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT7250 AND THE TERMINAL EQUIP- MENT (MODE 4 OPERATION) Terminal Equipment Signals RxOutClk Tx_Start_of_Frame E3_Nib_Clock_In E3_Data_Out[3:0] Payload Nibble [380] Overhead Nibble [0] XRT7250 Transmit Payload Data I/F Signals E3 Frame Number N E3 Frame Number N + 1 Note: TxNibFrame pulses high to denote E3 Frame Boundary. RxOutClk TxNibFrame TxNibClk TxNib[3:0] Nibble [380] Overhead Nibble [0] E3_Overhead_Ind TxOH_Ind TxOH_Ind pulses high for 3 Nibble periods FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) BIT 7BIT 6BIT 5BIT 4BIT 3BIT2 BIT 1 BIT 0 Local Loopback DS3/E3* Internal LOS Enable RESET Interrupt Enable Reset Frame Format TimRefSel[1:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0101 0 0 0 |
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