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XRT7250 Datasheet(PDF) 426 Page - Exar Corporation |
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XRT7250 Datasheet(HTML) 426 Page - Exar Corporation |
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426 / 463 page  áç áç áç áç XRT7250 DS3/E3 FRAMER IC REV. 1.1.1 407 Bit 1 (DL from NR) within the Rx E3 LAPD Control Register, as depicted below. Writing a “0” into this bit-field causes the LAPD Re- ceiver to read in the octets from the GC byte-field of each E3 frame and with these octets, reassembling the LAPD Message frame. Writing a “1” into this bit- field causes the LAPD Receiver to receive the LAPD Message frame octets from the NR byte-field of each E3 frame. 2. Enabling the LAPD Receiver The LAPD Receiver must be enabled before it can begin receiving and processing any LAPD Message frames. The LAPD Receiver can be enabled by writ- ing a “1” to Bit 2 (RxLAPD Enable) of the Rx E3 LAPD Control Register, as indicated below. Once the LAPD Receiver has been enabled, it will be- gin searching for the Flag Sequence octet (0x7E), in either the “GC” or the “NR” byte-fields within each in- coming E3 frame. When the LAPD Receiver finds the flag sequence byte, it will assert the Flag Present bit (Bit 0) within the Rx E3 LAPD Status Register, as de- picted below. The receipt of the Flag Sequence octet can mean one of two things. 1. This Flag Sequence byte may be marking the beginning or end of an incoming LAPD Message frame. 2. The Received Flag Sequence octet could be just one of many Flag Sequence octets that are trans- mitted via the E3 Transport Medium, during idle periods between the transmission of LAPD Mes- sage frames. The LAPD Receiver will negate the Flag Present bit as soon as it has received an octet that is something other than the Flag Sequence octet. Once this hap- pens, the LAPD Receiver should be receiving either octet # 2 of the incoming LAPD Message, or an ABORT Sequence (e.g., a string of seven or more consecutive “1’s”). If this next set of data is an RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18) BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0 Not Used DL from NR RxLAPD Enable RxLAPD Interrupt Enable RxLAPD Interrupt Status RO RO RO RO R/W R/W R/W RUR 0 0000 010 RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18) BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0 Not Used DL from NR RxLAPD Enable RxLAPD Interrupt Enable RxLAPD Interrupt Status RO RO RO RO R/W R/W R/W RUR 0 0000 110 RXE3 LAPD STATUS REGISTER (ADDRESS = 0X19) BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0 Not Used Rx ABORT RxLAPDType[1:0] RxCR Type RxFCS Error End of Message Flag Present RO RO RO RO RO RO RO RO 0 0000 001 |
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