KMA310 datasheet(22/71 Pages) NXP

22 / 71 page

NXP Semiconductors

KMA310

Programmable angle sensor IC

KMA310

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Product data sheet

Rev. 3 — 27 February 2019

22 / 71

Supply voltage State

Analog mode

SENT mode

Vth(on) or Vth(off)

to minimum VDD

functional

operation

All analog circuits are active and the

measured angle is available at the analog

output. Not all parameters are within the

specified limits.

All analog circuits are active and the

output is set to HIGH for at least 100 µs

before SENT transmission starts. Not all

parameters are within the specified limits.

Minimum VDD to

maximum VDD

normal

operation

All analog circuits are active and the

measured angle is available at the analog

output. All parameters are within the

specified limits.

All analog circuits are active and the

measured angle is available at the digital

output. All parameters are within the

specified limits.

Maximum VDD

to Vth(ov)

functional

operation

All analog circuits are active and the

measured angle is available at the analog

output. Not all parameters are within the

specified limits.

All analog circuits are active and the

measured angle is available at the digital

output. Not all parameters are within the

specified limits.

Vth(ov) to 18 V

overvoltage

The digital core and the oscillator are active

but all other circuits are in power-down

mode. The output is set to the lower

diagnostic level.

The digital core and the oscillator

are active but all other circuits are in

power-down mode. The output buffer

drives an active LOW.

Table 34 describes the diagnostic behavior and the resulting output voltage depending

on the error case. Furthermore the duration and termination condition to enter and leave

the diagnostic mode are given, respectively.

Table 34. Diagnostic behavior

Diagnostic condition

Duration

Output

Termination condition

Low voltage

20 µs < t < 120 µs ≤ 4 %VDD

functional or normal operation

Overvoltage

20 µs < t < 120 µs ≤ 4 %VDD

functional or normal operation

Checksum error

n.a.

≤ 4 %VDD or ≥ 96 %VDD[1]

power-on reset[2]

Double-bit error

n.a.

≤ 4 %VDD or ≥ 96 %VDD[1]

power-on reset[2]

Power-loss

≤ 2 ms

≤ 4 %VDD or ≥ 96 %VDD; see Table 32

power-on reset

[1]

Depending on the diagnostic level setting.

[2]

Status bit stays set in command register until power-on reset.

10.4 Oscillator monitoring (SM-13, SM-14 and SM-15)

If the oscillator frequency differs from the target frequency by more than ±30 % or the

oscillator stops, status bit 7 of CTRL1 register is set and the output goes into diagnostic

mode; see Table 50. If the oscillator frequency differs by more than ±10 %, the SENT

timing can violate the SAE J2716 SENT specification.

10.5 Safe assure - ASIL control unit

The ASIL control includes a state machine, which is a 4-bit up-counter that defines time

slots. The different time slots are used to trigger dedicated BISTs. To enable or disable

the complete ASIL control unit globally, use the BIST bit in ASIL_SETTING register; see

Table 51. The NVM register setting enables or disables individually each integrated test.

In case a self-test was performed a ready flag is generated to reset the start test trigger

signals. In case no reset signal is found, the output is set to diagnostic mode.

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