ADAV801 datasheet(45/56 Pages) AD

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ADAV801

Rev. 0 | Page 45 of 56

Table 58. DAC Control Register 2

RES

DMCLK1

DMCLK0

DFS1

DFS0

DEEM1

DEEM0

ADDRESS = 1100101 (0x65)

DMCLK1–0

DAC MCLK divider.

00 = MCLK.

01 = MCLK/1.5.

10 = MCLK/2.

11 = MCLK/3.

elect.

CLK

= 4 × (MCLK

128 × fS).

(MCLK = 64 × fS).

EEM1–0

elect.

10 = 32 kHz.

11 = 48 kHz.

DFS1–0

DAC interpolator s

00 = 8 × (M

= 256 × fS

10 = 2 ×

11 = Reserved.

DAC de-emphasis s

00 = None.

01 = 44.1 kHz.

Table 59. DAC Contr

RES

ZFVOL

ZFDATA

ZFPOL

RES

ADDRESS = 1100110 (0x66)

ZFVOL

DAC zero flag on mute and zero volume.

1 = Disabled.

disable.

0 = Enabled.

1 = Disabled.

lag polarity.

= Enabled.

ZFDATA

DAC zero flag on zero data

ZFPOL

DAC zero f

= Active high.

= Active low.

Table 60. DAC Contr

RES

INTRPT

ZEROSEL1

ZEROSEL0

RES

ol Register 4

ADDRESS = 1100111 (0x67)

INTRPT

This bit selects th

unctionality

the ZEROL/

pin.

e f

INT

0 = Pin functions as a ZEROL flag pin.

in.

lity of the ZEROR pin when the ZEROL/INT pin is used as an interrupt.

00 = Pin functions as a ZEROR flag pin.

01 = Pin functions as a ZEROL flag pin.

hen either the left or right channel is zero.

right channels are zero.

= Pin functions as an interrupt p

ZEROSEL1–0

hese bits control the functiona

0 = Pin is asserted w

1 = Pin is asserted when both the left and

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