97SD3232 datasheet(5/39 Pages) MAXWELL

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97SD3232

All data sheets are subject to change without notice

1 Gb (8-Meg X 32-Bit X 4-Banks) SDRAM

01.11.05 Rev 2

TABLE 5. AC Electrical Characteristics

CC =3.3V + 0.3V, VCCQ = 3.3V + 0.3V, TA = -55 TO 125° C, UNLESS OTHERWISE SPECIFIED)

PARAMETER

SYMBOL

SUBGROUPS

MIN

TYPICAL

MAX

UNIT

System clock cycle time1

(CAS latency = 2)

(CAS latency = 3)

9, 10, 11

7.5

CLK high pulse width1,7

CKH

9, 10, 11

2.5

CLK low pulse width1,7,

CKL

9, 10, 11

2.5

Access time from CLK1,2

(CAS latency = 2)

(CAS latency = 3)

9, 10, 11

Data-out hold time1,2,3

9, 10, 11

2.7

CLK to Data-out low impedance1,2,3,7

9, 10, 11

CLK to Data-out high impedance1,47,

(CAS latency = 2, 3)

9, 10, 11

5.4

Input setup time1,5,6

AS, tCS,

DS, tCES

9, 10, 11

1.5

CKE setup time for power down exit1

CESP

9, 10, 11

1.5

Input hold time1,6

AH, tCH, tDH

CEH

9, 10, 11

1.5

Ref/Active to Ref/Active command period1

9, 10, 11

Active to Precharge command period1

RAS

9, 10, 11

120000

Active command to column command 1

(same bank)

RCD

9, 10, 11

Precharge to Active command period1

9, 10, 11

Write recovery or data-in to precharge lead time1

DPL

9, 10, 11

Active( a) to Active (b) command period1

RRD

9, 10, 11

Transition time(rise and fall)7

9, 10, 11

Refresh Period

REF

9, 10, 11

6.4

@ 105 °C32

168

@ 85 °C64

@ 70 °C

128

1. AC measurement assumes t

T=1ns. Reference level for timing of input signals is 1.5V.

2. Access time is measured at 1.5V.

3. t

LZ(min) definesthe time at which the outputs achieve the low impedance state.

4. t

HZ(min) defines the time at which the outputs achieve the high impedance state.

5. tCES defines CKE setup time to CLK rising edge except for the power down exit command.

6. t

AS/tAH: Address, tCS/tCH: /RAS, /CAS, /WE, DQM

7. Guarenteed by design (Not tested).

8. Guarenteed by Device Charactreization Testing. (Not 100% Tested)

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