7872 datasheet(5/11 Pages) MAXWELL

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All data sheets are subject to change without notice

14-Bit A/D Converter

7872

5.21.02 Rev 4

TABLE 10. 7872 DC ELECTRICAL CHARACTERISTICS FOR POWER REQUIREMENTS

DD = 5V ± 5%, VSS = -5 V ± 5%, TA = -55 TO 125 ° C UNLESS OTHERWISE SPECIFIED)

PARAMETER

SYMBOL

CONDITIONS

REQUIREMENTS

UNITS

Positive Supply Voltage

5% for Specified Performance

Negative Supply Voltage

5% for Specified Performance

-5

Positive Supply Current

Typically 6mA

mA max

Negative Supply Current

Typically 4mA

mA max

Power Dissipation

Typically 50mW

mW max

TABLE 11. 7872 TIMING CHARACTERISTICS 1,2

DD = 5V ± 5%, VSS = -5 V ± 5%, TA = -55 TO 125 ° C UNLESS OTHERWISE SPECIFIED)

1. All input signals are specified with tr = tr = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2. Serial timing is measured with a 4.7 k

Ω pull-up resistor on SDATA and SSTRB and a 2 kΩ pull-up resistor on SCLK. The

capacitance on all three outputs is 35 pF.

PARAMETER/CONDITION

SYMBOL

SUBGROUPS

MIN

MAX

UNITS

CONVST Pulse Width

9, 10, 11

SSTRB to SCLK Falling Edge Setup Time

9, 10, 11

100

SCLK Cycle Time 3

3. SCLK mark/space ration (measured from a voltage level of 1.6 V) is 40/60 to 60/40.

9, 10, 11

440

SCLK to Valid Data Delay: C

L = 35 pF

4. SDATA will drive higher capacitive loads, but this will add to t

12 since it increases the external RC time constant (4.7kΩ/CL) and

hence, the time to reach 2.4 V.

9, 10, 11

155

SCLD Rising Edge to SSTRB

9, 10, 11

150

Bus Relinquish Time After SCLK

9, 10, 11

100

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