PXE1110C

PDS-PXE1-PXM1-C-001A

7

PXE1110 General Description

The PXE1110 digital dual rail 1+1 phase controller provides power for Intel® VR13 server applications. Users have

the option to order PXE1110 parts with either parallel-VID or SVID control. For parallel-VID parts, only one loop can

be set to follow the parallel-VID setting. The other loop will stay at Vboot. Users may set the VID of both loops

through I2C commands. Contact Infineon FAE for details.

Package Pin Designations

Table 7: PXE1110 Pin Descriptions

Pin #

Name

I/O

Type

Description

1

DNC

Do not connect (leave floating).

2

DNC

Do not connect (leave floating).

3

BPWM1

O

3.3V CMOS

Loop_B phase #1 PWM output. Refer to APWM1 description.

4

DNC

Do not connect (leave floating).

5

APWM1

O

3.3V CMOS

Loop_A phase #1 Pulse Width Modulation (PWM) output. This signal is

used to drive the PWM input of the power stage/FET driver IC. Unused

PWM pins should be left unconnected (floating).

6

SDA

I/O

Open Drain

SMBus/I2C bi-directional serial data signal.

7

SCL

I/O

Open Drain

SMBus/I2C bi-directional serial clock signal.

8

RESET#

I

3.3V CMOS

RESET# feature allows controller to be put into lowest power dissipation

mode. This pin may be left floating if unused but it is recommended that a

1kΩ pull up to 3.3V be used if this signal is connected to a trace on the

board.

9

AVRRDY

O

Open Drain

Voltage regulator “Ready” output signal. The AVRRDY indicator will be

asserted when the controller is ready to accept SVID commands after

AVREN is asserted. This open-drain output requires an external pull-up

resistor (1kΩ recommended). AVRRDY will be pulled low when a

shutdown fault occurs.

PXE1110

20

19

18

17

16

15

14

13

12

11

31

32

33

34

35

36

37

38

39

40

VD12

VDD

IINSEN

VINSEN

XADDR1

ATSEN

BTSEN

XADDR2

MP4

MP3

VRHOT#

PINALRT#

MP0

MP1

VCLK

VDIO

VALRT#

MP2

AVSEN

AVREF