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PDS-PXE1-PXM1-C-001A

10

PXM1310 General Description

The PXM1310 digital dual rail 3+1 phase controller provides power for Intel® VR13 memory applications. One output

voltage is provided by a 3-phase buck converter operating with up to three synchronous-rectified channels in

parallel while a single-phase buck converter provides voltage for the VPP rail.

Package Pin Designations

Table 8: PXM1310 Pin Descriptions

Pin #

Name

I/O

Type

Description

1

BPWM1

O

3.3V CMOS

Loop_B PWM output. Refer to APWM1 description.

2

DNC

Do not connect (leave floating).

3

APWM3

O

3.3V CMOS

Loop_A phase #3 PWM output. Refer to APWM1 description.

4

APWM2

O

3.3V CMOS

Loop_A phase #2 PWM output. Refer to APWM1 description.

5

APWM1

O

3.3V CMOS

Loop_A phase #1 Pulse Width Modulation (PWM) output. This signal is used

to drive the PWM input of the power stage/FET driver IC. Unused PWM pins

should be left unconnected (floating).

6

SDA

I/O

Open Drain

SMBus/I2C bi-directional serial data signal.

7

SCL

I/O

Open Drain

SMBus/I2C bi-directional serial clock signal.

8

RESET#

I

3.3V CMOS

RESET# feature allows controller to be put into lowest power dissipation

mode. This pin may be left floating if unused but it is recommended that a

1kΩ pull up to 3.3V be used if this signal is connected to a trace on the board.

9

AVRRDY

O

Open Drain

Voltage regulator “Ready” output signal. The AVRRDY indicator will be

asserted when the controller is ready to accept SVID commands after

AVREN is asserted. This open-drain output requires an external pull-up

resistor (1kΩ recommended). AVRRDY will be pulled low when a shutdown

fault occurs.

PXM1310

20

19

18

17

16

15

14

13

12

11

31

32

33

34

35

36

37

38

39

40

VD12

VDD

IINSEN

VINSEN

XADDR1

ATSEN

BTSEN

XADDR2

BISEN1

BIREF1

VRHOT#

PINALRT#

MP0

MP1

VCLK

VDIO

VALRT#

MP2

AVSEN

AVREF