VSC7440 datasheet(440/444 Pages) MICROSEMI

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Design Guidelines

VMDS-10492 VSC7440 Datasheet Revision 4.2

423

•

Low swing signaling is supported for VDD_VS = 1.2 V and VDD_VS =1.0 V.

During PCIe startup (VCORE_CFG = 1001), only low swing signaling with no de-emphasis is supported,

regardless of the VDD_VS voltage. After startup, configure the PCIe interface as desired.

9.3.5

Two-Wire Serial Interface

The two-wire serial interface is capable of suppressing small amplitude glitches less than 5 ns in

duration, which is less than the 50 ns duration often quoted for similar interfaces. Because the two-wire

serial implementation uses Schmitt-triggered inputs, the VSC7440 device has a greater tolerance to low

amplitude noise. For glitch-free operation, select the proper pull-up resistor value to ensure that the

transition time through the input switching region is less than 5 ns given the line’s total capacitive load.

For capacitive loads up to 40 pF, a pull-up resistor of 510

Ω or less ensures glitch-free operation for noise

levels up to 700 mV peak-to-peak.

9.3.6

DDR3 SDRAM Interface

The DDR3 SDRAM interface is designed to interface with 8-bit or 16-bit DDR SDRAM devices. The

maximum amount of physical memory that can be addressed is one gigabyte. Possible combinations of

memory modules are:

•

One 8-bit device, connect to CS0 byte lane 0.

•

Two 8-bit devices, connect to CS0 and both byte lanes.

•

Four 8-bit devices, connect to both chip-selects and both byte lanes.

•

One 16-bit device, connect to CS0 and both byte lanes.

•

Two 16-bit devices, connect to both chip-selects and both byte lanes.

When using a single 8-bit device, the memory controller must be configured for 8-bit mode. All other

configurations use 16-bit mode.

All signals on this interface must be connected one-to-one with the corresponding signals on the DDR

SDRAM device. When using only one 8-bit device, the DDR_UDQS, DDR_UDQSn, DDR_UDM, and

DDR_DQ[15:8] signals must be left unconnected. When using DDR2 SDRAM devices that has only four

banks, the DDR_BA[2] signal must be left unconnected.

When using four 8-bit devices or two 16-bit devices, the CS1 memory modules must be placed in-

between the VSC7440 device and the CS0 memory modules so that the DDR-DQS, DDR-DM, and

DDR_DQ signals pass the CS1 devices first before reaching the CS0 devices.

The placement of the VSC7440 interface signals is optimized for point-to-point routing directly to a single

DDR3 16-bit SDRAM.

Figure 155 •

16-Bit DDR3 SDRAM Point-to-Point Routing

Because reflections are absorbed by the devices, keep the physical distance of all the SDRAM interface

signals as low as possible. Omit external discrete termination on the address, command, control and

clock lines.

DRAM

Device

Switch

Address

Clock

Address

Data Lane

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