VSC7440 datasheet(437/444 Pages) MICROSEMI

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Design Guidelines

VMDS-10492 VSC7440 Datasheet Revision 4.2

420

Design Guidelines

This section provides information about design guidelines for the VSC7440 device.

9.1

Power Supplies

The following guidelines apply to designing power supplies for use with the VSC7440 device.

•

Make at least one unbroken ground plane (GND).

•

Use the power and ground plane combination as an effective power supply bypass capacitor. The

capacitance is proportional to the area of the two planes and inversely proportional to the separation

between the planes. Typical values with a 0.25 mm (0.01 inch) separation are 100 pF/in2. This

capacitance is more effective than a capacitor of equivalent value, because the planes have no

inductance or Equivalent Series Resistance (ESR).

•

Do not cut up the power or ground planes in an effort to steer current paths. This usually produces

more noise, not less. Furthermore, place vias and clearances in a configuration that maintains the

integrity of the plane. Groups of vias spaced close together often overlap clearances. This can form

a large slot in the plane. As a result, return currents are forced around the slot, which increases the

loop area and EMI emissions. Signals should never be placed on a ground plane, because the

resulting slot forces return currents around the slot.

•

Vias connecting power planes to the supply and ground balls must be at least 0.25 mm (0.010 inch)

in diameter, preferably with no thermal relief and plated closed with copper or solder. Use separate

(or even multiple) vias for each supply and ground ball.

9.2

Power Supply Decoupling

Each power supply voltage should have both bulk and high-frequency decoupling capacitors.

Recommended capacitors are as follows:

•

For bulk decoupling, use 10 µF high capacity and low ESR capacitors or equivalent, distributed

across the board.

•

For high-frequency decoupling, use 0.1 µF high frequency (for example, X7R) ceramic capacitors

placed on the side of the PCB closest to the plane being decoupled, and as close as possible to the

power ball. A larger value in the same housing unit produces even better results.

•

Use surface-mounted components for lower lead inductance and pad capacitance. Smaller form

factor components are best (that is, 0402 is better than 0603).

9.2.1

Reference Clock

The device reference clock can be a 25 MHz, 125 MHz, 156.25 MHz, or 250 MHz clock signal. It can be

either a differential reference clock or a single-ended clock. For more information, see Reference Clock,

page 371.

9.2.2

Single-Ended REFCLK Input

An external resistor network is required to use a single-ended reference clock. The network limits the

amplitude and adjusts the center of the swing. Depending on the clock driver output impedance, the

resistor values may need to be adjusted so that the REFCLK_P signal meets requirements. For

information about these requirements, see Table 275, page 371.

The following illustrations show configurations for a single-ended reference clock.

VSC7440 Datasheet(PDF) 437 Page - Microsemi Corporation

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