VSC7440 datasheet(438/444 Pages) MICROSEMI

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Design Guidelines

VMDS-10492 VSC7440 Datasheet Revision 4.2

421

Figure 153 •

2.5 V CMOS Single-Ended REFCLK Input Resistor Network

Figure 154 •

3.3 V CMOS Single-Ended REFCLK Input Resistor Network

9.3

Interfaces

This section provides general recommendations for all interfaces and information related to the specific

interfaces on the device.

9.3.1

General Recommendations

High-speed signals require excellent frequency and phase response up to the third harmonic. The best

designs provide excellent frequency and phase response up to the seventh harmonic. The following

recommendations can improve signal quality and minimize transmission distances:

•

Keep traces as short as possible. Initial component placement should be considered very carefully.

•

The impedance of the traces must match the impedance of the termination resistors, connectors,

and cable. This reduces reflections due to impedance mismatches.

•

Differential impedance must be maintained in a 100

Ω differential application. Routing two 50 Ω

traces is not adequate. The two traces must be separated by enough distance to maintain differential

impedance. When routing differential pairs, keep the two trace lengths identical. Differences in trace

lengths translate directly into signal skew. Note that the differential impedance may be affected when

separations occur.

•

Keep differential pair traces on the same layer of the PCB to minimize impedance discontinuities. In

other words, avoid using vias.

•

Do not group all the passive components together. The pads of the components add capacitance to

the traces. At the frequencies encountered, this can result in unwanted reductions in impedance.

Use surface-mounted 0603 (or smaller) components to reduce this effect.

•

Eliminate or reduce stub lengths.

•

Reduce, if not eliminate, vias to minimize impedance discontinuities. Remember that vias and their

clearance holes in the power/ground planes can cause impedance discontinuities in nearby signals.

Keep vias away from other traces.

•

Keep signal traces away from other signals that might capacitively couple noise into the signals. A

good rule of thumb is to keep the traces apart by ten times the width of the trace.

•

Do not route digital signals from other circuits across the area of the high-speed transmitter and

receiver signals.

•

Using grounded guard traces is typically not effective for improving signal quality. A ground plane is

more effective. However, a common use of guard traces is to route them during the layout, but

remove them prior to design completion. This has the benefit of enforcing keep-out areas around

sensitive high-speed signals so that vias and other traces are not accidentally placed incorrectly.

470

510

REFCLK_P

REFCLK_N

2.5 V

CMOS

Floating

VSS

VDD_A

560

390

REFCLK_P

3.3 V

CMOS

REFCLK_N

Floating

VDD_A

VSS

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