VSC7440 datasheet(439/444 Pages) MICROSEMI

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Design Guidelines

VMDS-10492 VSC7440 Datasheet Revision 4.2

422

•

When signals in a differential pair are mismatched, the result is a common-mode current. In a well-

designed system, common-mode currents should make up less than one percent of the total

differential currents. Mode currents represent a primary source of EMI emissions. To reduce

common-mode currents, route differential traces so that their lengths are the same. For example, a

5-mm (0.2-inch) length mismatch between differential signals having the rise and fall times of 200 ps

results in the common-mode current being up to 18% of the differential current.

Note: Care must be taken when choosing proper components (such as the termination resistors) in the

designing of the layout of a printed circuit board, because of the high application frequency. The use of

surface-mount components is highly recommended to minimize parasitic inductance and lead length of

the termination resistor.

Matching the impedance of the PCB traces, connectors, and balanced interconnect media is also highly

recommended. Impedance variations along the entire interconnect path must be minimized, because

they degrade the signal path and may cause reflections of the signal.

9.3.2

SerDes Interfaces (SGMII, 2.5G, 10G)

The SGMII interface consists of a Tx and Rx differential pair operating at 1250 Mbps. The 2.5G interface

consists of a Tx and Rx differential pair operating at 3125 Mbps. The 10G interface consists of a Tx and

Rx differential pair typically operating at 10.3125 Mbps.

The SerDes signals can be routed on any PCB trace layer with the following constraints:

•

Tx output signals in a pair should have matched electrical lengths. 10G pairs should match to <<

1mm.

•

Rx input signals in a pair should have matched electrical lengths. 10G pairs should match to <<

1mm.

•

SerDes Tx and Rx pairs must be routed as 100

Ω differential traces with ground plane as reference.

•

Keep differential pair traces on the same layer of the PCB to minimize impedance discontinuities. In

other words, avoid the use of vias wherever possible.

•

AC-coupling of Tx and Rx may be needed, depending on the attached PHY or module. External AC-

coupling is recommended for use with most PHYs. SFP and SFP+ modules have internal AC-

coupling, so they do not require additional AC-coupling capacitors. If AC-coupled, the VSC7440

SerDes inputs are self-biased. It is recommended to use small form factor capacitors, 0402 or

smaller, to reduce the impedance mismatch caused by the capacitor pads.

•

To reduce the crosstalk between pairs or other PCB lines, it is recommended that the spacing on

each side of the pair be larger than four times the track width. The characteristic impedance of the

pairs must predominantly be determined by the distance to the reference plane, and not the distance

to neighboring traces.

9.3.3

Serial Interface

If the serial CPU interface is not used, all input signals can be left floating.

The SI bus consists of the SI_CLK clock signal, the SI_DO and SI_DI data signals, and the SI_nCS0

device select signal.

When routing the SI_CLK signal, be sure to create clean edges. If the SI bus is connected to more than

one slave device, route it in a daisy-chain configuration with no stubs. Terminate the SI_CLK signal

properly to avoid reflections and double clocking.

If it is not possible (or desirable) to route the bus in a daisy-chain configuration, the SI_CLK signal should

be buffered and routed in a star topology from the buffers. Each buffered clock should be terminated at its

source.

9.3.4

PCI Express Interface

The VSC7440 device does not accept spread spectrum modulated PCIe input. Although the device only

supports PCI Express Base Specification Revision 1.1, the PCIe transmitter and receiver support the PCI

Express Base Specification Revision 2.0 Electrical sub-block specifications under the following

conditions:

•

Only 2.5 gigatransfers per second (GT/s) is supported.

•

Full swing output signaling is only supported when VDD_VS =1.2 V.

VSC7440 Datasheet(PDF) 439 Page - Microsemi Corporation

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