VSC7511 datasheet(189/324 Pages) MICROSEMI

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VCore-Ie System and CPU Interfaces

VMDS-10488 VSC7511 Datasheet Revision 4.2

174

A 32-bit switch core register read or write transaction over the MIIM interface is done indirectly due to the

limited data width of the MIIM frame. First, the address of the register inside the device must be set in the

two 16-bit address registers of the MIIM slave using two MIIM write transactions. The two 16-bit data

registers can then be read or written to access the data value of the register inside the device. Thus, it

requires up to four MIIM transactions to perform a single read or write operation on a register target.

The address of the register to read/write is set in registers ADDR_REG0 and ADDR_REG1. The data to

write to the register pointed to by the address in ADDR_REG0 and ADDR_REG1 is first written to

DATA_REG0 and then to DATA_REG1. When the write transaction to DATA_REG1 is completed, the

MIIM slave initiates the switch core register write.

With the register address of a specific register (REG_ADDR), the MIIM address (MIIM_ADDR) is

calculated as:

MIIM_ADDR = (REG_ADDR & 0x00FFFFFF)>>2

The following illustration shows a single MIIM write transaction on the MIIM interface.

Figure 64 •

MIIM Slave Write Sequence

A read transaction is done in a similar way. First, read the DATA_REG0 and then read the DATA_REG1.

As with a write operation. The switch core register read is not initiated before the DATA_REG1 register is

read. In other words, the returned read value is from the previous read transaction.

The following illustration shows a single MIIM read transaction on the MIIM interface.

Figure 65 •

MIIM Slave Read Sequence

STAT_REG

The status register gives the status of any ongoing

operations.

Bit 0: Busy. Set while a register read/write operation is

in progress.

Bit 1: Busy_rd. Busy status during the last read or write

operation.

Bit 2: Err. Set if a register access error occurred.

Others: Reserved.

Table 138 •

MIIM Registers (continued)

Description

MDC

MDIO

PREAMBLE

32 bit

2 bit

PHYAD

5 bit

REGAD

5 bit

2 bit

DATA

16 bit

MDC

MDIO

PREAMBLE

32 bit

2 bit

PHYAD

5 bit

REGAD

5 bit

2 bit

DATA

16 bit

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